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1. 发明专利

JPH10194376A TRAY WITH CARRIER AND PROTECTIVE SHEET, AND TRAY 失效
公开(公告)号：JPH10194376A
公开(公告)日：1998-07-28
申请号：JP256097
申请日：1997-01-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , TSUBOI KAZUYA , NUMAZAKI MASAHITO , OKINAGA TAKAYUKI , OTSUKA KENICHI , ENOMOTO USUKE
IPC分类号： B65D85/86 , H01L21/673 , H01L21/68
摘要： PROBLEM TO BE SOLVED: To improve workability of assembly and to prevent breakage and staining from occurring by providing a sheet-like tray with a recessed storing cavities, a freely removable fixing tool to be laminated and integrally fixed, and providing positional slip preventing parts on the tray. SOLUTION: Positional slip preventing parts 20 prevent positional slip of a protective sheet 6 from occurring and are provided on the corners of a rectangular fitting part 11 on the top face of which a plurality of storing cavities 7 are provided so as to be projected. In addition, they guide the corners of the rectangular protective sheet 6 and are L-shaped guide pieces 21 opened by 90 degrees. The stop movement of the protective sheet 6 placed on the top face of a tray along the top face of the tray, the height of the guide pieces 21 is a dimension the same as or larger than the thickness of the protective sheet 6. A fitting cavity is provided on the underside of the tray 2. The tray 2 is laminated in the fitting cavity and the fitting cavity 11 of the lower side tray 2 is fitted therein. As escape cavities in which the top end parts of the guide pieces 21 enter are provided on the bottom, there exists no possibility of direct contact with the upper tray 2.

2. 发明专利

JPH1078455A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1078455A
公开(公告)日：1998-03-24
申请号：JP23390996
申请日：1996-09-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , OKINAGA TAKAYUKI , OTA MITSUNORI , KAWAKAMI MASAMI , HAYASHI MAKOTO , MARUYAMA SHIGENORI
IPC分类号： G01R31/26 , G01R1/073 , H01L21/66 , H05K1/11 , H05K3/32
摘要： PROBLEM TO BE SOLVED: To rapidly test many types of semiconductor devices with a low cost by providing leader wirings at narrower pitch than an interval of external leads of the devices on a main surface of a test board, and commonly using the board. SOLUTION: Fine wirings 3 are formed at a narrower pitch than an interval between leads 1b of a semiconductor device 1a on a main surface of a test board 2 by depositing or thick-film wiring plating. Thus, the same board 2 can be used for various devices 1a having different lead interval or lead shape or further the semiconductor device having different package size. Accordingly, a special purpose socket is eliminated, and further since placing the device 1b on the board 2 is simplified due to placing on the flat board, a rapid test can be executed.

3. 发明专利

JPH08330351A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08330351A
公开(公告)日：1996-12-13
申请号：JP13041095
申请日：1995-05-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MAKINO SATOSHI , YOSHIDA NOBUO , SHIRAI MASAYUKI , OKINAGA TAKAYUKI , KIKUCHI YOSHIFUMI
IPC分类号： H01L21/60
摘要： PURPOSE: To completely prevent the wires, which connects the bonding pad of a semiconductor chip and the inner lead of a lead frame, from coming into contact with each other in a multipin LSI package by a method wherein the bonding pads on the inner circumferential side and the bonding pads on the outer circumferential side are arranged in zigzags. CONSTITUTION: Bonding pads 7 are connected to buffer circuits 8 respectively through wirings 10. The bonding pads 7 are arranged in zigzags, and wires 6, with which the bonding pads 7 on the inner circumferential side and leads 5 are connected, pass through almost middle of the two bonding pads 7 on the outer circumferential side neighboring to the bonding pads 7 on the inner circumferential side of the wires 6. Besides, the extended part of the wires 6, which connect the outer circumferential side bonding pads 7 and the leads 5, are arranged in such a manner that they pass through almost middle of the two bonding pads 7 on the inner circumferential side adjacent to the bonding pads 7 on the circumferential side.

4. 发明专利

JPH08300394A MOLD AND MOLDING OF RESIN SEAL ELEMENT USING THE SAME 失效
公开(公告)号：JPH08300394A
公开(公告)日：1996-11-19
申请号：JP10507695
申请日：1995-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HORIUCHI HITOSHI , TATE HIROSHI , OKINAGA TAKAYUKI , EMATA KOJI , SASAKI MASAKO , NOSE FUJIAKI , HONDA ATSUSHI
IPC分类号： B29C45/26 , B29C45/02 , B29C45/14 , B29L31/34 , H01L21/56
摘要： PURPOSE: To provide a mold preventing trouble such that the resin supplied into a cavity transfers to one surface of a plate-shaped article and to prevent the molding inferiority of a resin seal element to which one surface of the plate-shaped article is exposed. CONSTITUTION: In a mold 1 equipped with a cavity 2 having a plate-shaped article 14 mounted on the mounting region of the bottom surface 2A thereof, a recessed part, 3 is formed to the central part of the mounting region of the bottom surface 2A of the cavity 2. In a method for molding a resin seal element 10 wherein one surface of the plate-shaped article 14 is exposed, a stage preparing the mold 1 having the cavity 2 constituting the recessed part 3 at the central part of the mounting region of the bottom surface 2A on which the plate-shaped article 14 is mounted, a stage mounting the plate-shaped article 14 to the mounting region of the bottom surface of the cavity 2 and a stage supplying a resin 10 into the cavity 2 are provided.

5. 发明专利

JPH08227903A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH08227903A
公开(公告)日：1996-09-03
申请号：JP34237495
申请日：1995-12-28
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： OKINAGA TAKAYUKI , TATE HIROSHI , OZAKI HIROSHI , OTSUKA KANJI , FURUKAWA MICHIAKI , YAMAZAKI YASUYUKI
IPC分类号： H01L21/52 , H01L21/56 , H01L21/60 , H01L23/50
摘要： PURPOSE: To enhance the bonding strength between the resin of a package and the lead even for a semiconductor device mounting a large pellet by providing a first lead traversing one side of a semiconductor pellet toward a bonding pad, and a second lead traversing the extension of one side and facing the bonding pad. CONSTITUTION: Outer leads are arranged on the side of a pellet where the bonding pad is not arranged and the inner leads of the leads 2a are extended along the major surface of the pellet 1 where the circuit is not formed. The forward end 2b thereof is extended over the side of the pellet where bonding pads 7 are arranged. Since the inner lead of the lead 2a is very long, bonding strength can be enhanced significantly between the lead and the package resin 4. Furthermore, even when a large pellet is mounted, delamination can be prevented effectively at the interface of lead when the outer lead is bent, for example.

6. 发明专利

JPH08115997A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08115997A
公开(公告)日：1996-05-07
申请号：JP24663494
申请日：1994-10-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , TATE HIROSHI , HORIUCHI HITOSHI , NISHIUMA MASAHIKO , OGUMA HIROSHI , KOMATA MAKOTO , SASAKI MASAKO , OKINAGA TAKAYUKI
IPC分类号： H01L21/60 , H01L23/12 , H05K3/34
摘要： PURPOSE: To provide a semiconductor device, in which there is no unconnected bump of and no bridge failure, the establishment of its inspection method is not necessary and the thermal fatigue life of connection parts is prolonged. CONSTITUTION: A semiconductor chip 1, on the surface of which terminals (pads) 2 are formed, is fixed to a wiring board 3 that is made of an insulating material like resin or ceramic with an adhesive. Conductive parts 5, each of which comprises a wiring pattern that extends from the front surface to the rear surface of the wiring board 3 via through holes 4, are formed. On the conductive parts 5 on the rear surface of the wiring board 3, conductor balls 8 are provided in a lattice, forming a BGA structure. On each of the conductor balls 8, a conductive layer is formed by plating or printing. The conductor balls 8 that serve as bumps are selected to be of uniform diameter beforehand and the material of the conductor balls 8 has a higher melting point than the softening point of the wiring board 3 or the mounting board to which the wiring board 3 is connected.

7. 发明专利

JPH05229584A TRAY FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH05229584A
公开(公告)日：1993-09-07
申请号：JP3736092
申请日：1992-02-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KOMATA MAKOTO , EMATA KOJI , OKINAGA TAKAYUKI , NISHIUMA MASAHIKO , HORIUCHI HITOSHI , OTSUKA KANJI , HONDA ATSUSHI
IPC分类号： B65D85/00 , B65D85/38 , B65D85/86 , H01L21/673 , H01L21/68
摘要： PURPOSE:To prevent the bending of leads of QFP (Thin Quad Flat Package) stored in a tray during transportation. CONSTITUTION:A tray 1 for a semiconductor device is provided with a projection 3 at each corner of a storing part 2 for receiving QFP 6 and each projection 3 is provided at its end with a groove 4, with which the corner of a package body 7 is engageable, whereby QFP 6 can be accurately secured in the storing part 2.

8. 发明专利

JPH04249349A SEMICONDUCTOR DEVICE AND MANUFACTURE THERE 失效
公开(公告)号：JPH04249349A
公开(公告)日：1992-09-04
申请号：JP1460791
申请日：1991-02-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIRAI MASAYUKI , OTSUKA KANJI , MIYAZAKI KUNIO , SATSUU YUUICHI , MIURA OSAMU , OKINAGA TAKAYUKI , EMATA KOJI , HORIUCHI HITOSHI , UCHIUMI YASUYUKI , MIWA TAKASHI
IPC分类号： H01L21/56 , H01L21/60 , H01L23/29 , H01L23/31
摘要： PURPOSE:To improve a resin sealed semiconductor device and a manufacturing method thereof concerning the reliability. CONSTITUTION:A single film layer of a silane coupling agent is deposited, at the covering ratio of 1exp-5 through 1, over the surface of components 10, 14 and 12 of a plastic seal semiconductor device. In the manufacturing method for this semiconductor device, the amount of the silane coupling agent sufficient to coat the surface of the components 10, 14, 12 is dispersed in vapor phase, or in liquid phase, and the elements are subjected to a coupling process in the liquid or the vapor phase. The deposition, or the formation, of a monomolecular layer of the silane coupling film leads to an improvement in the strength of joint between the plastic seal and the components, whereby the semiconductor device and the manufacturing method thereof can be enhanced with respect to the reliability.

9. 发明专利

JPH02196454A SEMICONDUCTOR PACKAGE 失效
公开(公告)号：JPH02196454A
公开(公告)日：1990-08-03
申请号：JP1397389
申请日：1989-01-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OKINAGA TAKAYUKI , OTSUKA KANJI , UCHIUMI YASUYUKI , MATSUGAMI SHOJI
IPC分类号： H05K7/20 , H01L23/467
摘要： PURPOSE:To eliminate the necessity of a cooling system of a large scale, to eliminate deviation in heat distribution and to enable an effective heat design by providing a semiconductor package itself with a radiator to dissipate heat on the surface of the package. CONSTITUTION:A radiator 9 to dissipate heat on a surface of a semiconductor package 1 is attached to the package 1 itself which is airtightly sealed or resin- sealed. A cooling means is provided to the semiconductor package 1 itself to cool the semiconductor package 1 itself by the radiator 9. Therefore, the semiconductor package 1 is constituted so that it can be cooled without requiring a heat dissipation means such as an air cooling radiating fan besides the radiator 9. For example, a cooling fan 12 is contained inside a radiation base 10 of the radiator 9, and the cooling fan 12 is interconnected with a driving motor 13 which is provided to an upper part of the radiation base 10 through a driving shaft 14 at a center of the radiation base 10, and revolves inside the radiation base 10 through an operation of the driving motor 13 to diffuse heat produced on a surface of a package base 2 and to release it externally through an open window 11.

10. 发明专利

JPH02170559A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02170559A
公开(公告)日：1990-07-02
申请号：JP32566188
申请日：1988-12-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： EMATA KOJI , SHIRAI MASAYUKI , OTSUKA KANJI , OKINAGA TAKAYUKI , AKASAKI HIROSHI
IPC分类号： H01L23/06 , H01L23/50
摘要： PURPOSE:To decrease the growth speed of migration between wiring patterns and to improve a semiconductor device of this design in service life by a method wherein a space between the wiring patterns is made large in a region which extends from the position of a lead pin to the end face of an insulating board. CONSTITUTION:A space between adjacent wiring patterns 8 is made large in a region which extends from the position of a lead pin 10, which is droopingly provided at the outermost periphery of a insulating board, out of inserted lead pins 10 to the outer end face of the insulating board. Three wiring patterns 8 are formed between the lead pins 10 adjacent to each other, the right wiring pattern 8 is bent to the right side, and the left wiring pattern 8 is bent to the left side. Therefore, spaces L1-L4 between five wiring patterns 8 are all the same. By this setup, a migration growth speed can be controlled, so that a semiconductor device of this design can be lengthened in service life and made to be one provided with a super-large number of lead pins.

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