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1. 发明专利

JPH08339947A MANUFACTURE OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER USED THEREIN AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08339947A
公开(公告)日：1996-12-24
申请号：JP16819095
申请日：1995-06-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO TOMOMI , SUZUKI NORIO , SHIMIZU HIROBUMI , KOIKE ATSUYOSHI , MAEJIMA HIROSHI , KANAI AKIRA
IPC分类号： H01L21/67 , B24B9/06 , B24B49/12 , H01L21/02 , H01L21/304 , H01L21/68
摘要： PURPOSE: To discriminate between a front and a rear while keeping a symmetry of notch plane configuration by making a chamfered part formed in an inner circumferential edge part of one main surface and a chamfered part formed in an inner circumferential edge part of the other main surface in a notch formed in a circumference part differ from each other. CONSTITUTION: A first notch chamfered part 11 is formed in an inner circumferential edge part of a first main surface 3 of a notch 10 and a second notch chamfered part 12 is formed in an inner circumferential edge part of a second main surface 4 of the notch 10. The first notch chamfered part 11 and the second notch chamfered part 12 are formed to show non-plane symmetry regarding a central surface in a thickness direction of the notch 10. It is possible to discriminate between the first main surface 3 and the second main surface 4 of a wafer 1 with a notch by discriminating between the first notch chamfered part 11 and the second notch chamfered part 12 in this way.

2. 发明专利

JPH09246130A SEMICONDUCTOR WAFER, MANUFACTURE THEREOF, AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH09246130A
公开(公告)日：1997-09-19
申请号：JP7839796
申请日：1996-03-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KANAI AKIRA , SHIMIZU HIROBUMI , SATO TOMOMI , SUZUKI NORIO
IPC分类号： H01L21/68 , H01L21/02 , H01L21/322 , H01S3/00 , H01S5/00 , H01S3/18
摘要： PROBLEM TO BE SOLVED: To provide a round wafer such that the position and crystallographic axis direction may be identified. SOLUTION: A manufacturing method of a round wafer 1 includes a longitudinal groove forming process for providing a longitudinal groove 12 in a predetermined crystal surface orientation of a block 11 ground in a columnar shape from a semiconductor ingot, a slicing process for cutting a thin plate 13 having a V-groove 14 from the block provided with the longitudinal groove, a singular property part forming process for forming a melting mark 18 having different property from other parts by irradiating the inner side of the V-groove of the thin plate with a laser 16, and a characteristic part forming process for removing the V-groove, then planarizing the main surface of the melting mark 18 and thus locally forming a characteristic part 5 having a flat surface and a different inner lattice strain 19 from the other parts, on a round semiconductor substrate 2. Thus, the round wafer may be aligned by detecting the characteristic part. With this round wafer, disorder in gas flow and thermal stress dislocation may be prevented at the time of IC manufacturing. Since the characteristic part has the inner property differing only locally, no deterioration in yield is generated.

3. 发明专利

DE3112186A1 未知
公开(公告)号：DE3112186A1
公开(公告)日：1982-01-28
申请号：DE3112186
申请日：1981-03-27
申请人： HITACHI LTD
发明人： TOCHIKUBO HIROO , KANAI AKIRA
IPC分类号： C30B1/02 , C30B29/06 , H01L21/20
摘要： Herein disclosed is a method of fabricating a thick single-crystalline silicon film at a low temperature less than 1000 DEG C. The method is characterized in that, simultaneously as silicon polycrystals are grown on a substrate to form polycrystalline silicon, said polycrystals are irradiated and annealed with a laser or electron beam so that said polycrystalline silicon is single-crystallized to fabricate a single-crystalline silicon film.

4. 发明专利

JP2585642B2 失效
公开(公告)号：JP2585642B2
公开(公告)日：1997-02-26
申请号：JP28622887
申请日：1987-11-12
申请人： HITACHI LTD
发明人： KANAI AKIRA , UMEMURA NOBUAKI
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L27/06 , H01L29/04 , H01L29/72 , H01L29/73 , H01L29/732

5. 发明专利

JPH04150035A SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH04150035A
公开(公告)日：1992-05-22
申请号：JP27484190
申请日：1990-10-12
申请人： HITACHI LTD
发明人： SAIDA HIROJI , TAKAHASHI KENJI , UMEMURA NOBUAKI , KANAI AKIRA
IPC分类号： H01L29/73 , H01L21/304 , H01L21/322 , H01L21/331 , H01L21/8238 , H01L27/092 , H01L29/732 , H01L29/78
摘要： PURPOSE:To form a semiconductor substrate at a low impurity concentration by a method wherein, when an n-type epitaxial layer is grown, piled-up impurities or a denatured layer are polished and removed down to a prescribed depth by a polishing technique. CONSTITUTION:An n-type epitaxial layer 11 whose impurity concentration is lower than the impurity concentration of an n type semiconductor substrate 10 is grown in a prescribed film thickness on the main face of the substrate 10; partial impurities existing on the surface of the layer 11 or a denatured layer 12 are polished and removed down to a prescribed depth by a polishing technique so that the impurities are not piled up again. Then, an insulating film 5 is formed on the polished surface; a series of processes is executed after that; a transistor is constituted. Thereby, the layer in which the impurities exist in large quantities is removed, the semiconductor substrate can be formed at a low impurity concentration and a MISFET for high breakdown strength can be obtained.

6. 发明专利

JPS6314273B2 失效
公开(公告)号：JPS6314273B2
公开(公告)日：1988-03-30
申请号：JP7139880
申请日：1980-05-30
申请人： HITACHI LTD
发明人： KANAI AKIRA , TOCHIKUBO HIROO
IPC分类号： F26B21/14

7. 发明专利

JPS62122276A MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62122276A
公开(公告)日：1987-06-03
申请号：JP26112885
申请日：1985-11-22
申请人： HITACHI LTD
发明人： INABA KEIZO , TOCHIKUBO HIROO , SHIMIZU SHUICHI , KANAI AKIRA
IPC分类号： H01L21/205 , H01L21/338 , H01L29/80 , H01L29/812
摘要： PURPOSE:To obtain the manufacturing method of a GaAs FFT characterized by no dispersion in threshold voltage VTH and source-drain current IDSS, by forming an active layer having a required thickness on a substrate, and partially forming a high-concentration semiconductor layer, which is ohmic-contacted with source and drain electrodes, on the active layer by a selective epitaxial method. CONSTITUTION:On one main surface of a GaAs substrate 1, a gate electrode G comprising metal, which forms a Schottky barrier, and source and drain electrodes comprising metal, which is ohmic-contacted with the substrate so as to hold the gate in-between, are formed. In this manufacturing method of GaAs FET, an n-type active layer 3 having a required thickness is formed on the GaAs substrate 1. A high-concentration n type layer 9, which is ohmic- contacted with the source and drain electrodes, is partially formed on the active layer by a selective epitaxial method. Thus the gate electrode G is formed on the n-type active layer 3, which has a substantially recessed shape. Thus the width of the active layer directly beneath the gate can be controlled, and dispersion in VTH and the like can be reduced.

8. 发明专利

JPS5650508A MANUFACTURE MONOCRYSTALLING SEMICONDUCTOR SUBSTRATE AND ITS 失效
公开(公告)号：JPS5650508A
公开(公告)日：1981-05-07
申请号：JP12539579
申请日：1979-10-01
申请人： HITACHI LTD
发明人： KANAI AKIRA , TOCHIKUBO HIROO , KASE YUUSHI
IPC分类号： H01L21/205
摘要： PURPOSE:To obtain a semiconductor substrate having extremely scanty density of carbon, oxygen and having no generation of swirl defect by a method wherein a monocrystalline semiconductor substrate is formed only with an epitaxial growth layer. CONSTITUTION:An epitaxial growth layer 3 is formed on the main face of a monocrystalline semiconductor plane material 1, and the material 1 is removed to manufacture a monocrystalline semiconductor substrate 4 consisting of only the epitaxial growth layer 3. Accordingly, a monocrystalline semiconductor substrate having extremely scanty density of carbon, oxygen and having no generation of swirl defect can be obtained.

9. 发明专利

JPH0354814A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0354814A
公开(公告)日：1991-03-08
申请号：JP2957290
申请日：1990-02-13
申请人： HITACHI LTD
发明人： KANAI AKIRA , TOCHIKUBO HIROO
IPC分类号： H01L21/74 , H01L21/027 , H01L21/30
摘要： PURPOSE:To improve the accuracy of mask alignment for a buried layer formed in a semiconductor substrate partially by a method wherein an infrared beam is applied onto the main surface of the semiconductor substrate and the reflective image of the buried layer obtained by the beam application is detected and used as the reference for the mask alignment. CONSTITUTION:An epitaxial semiconductor layer 4 is formed on a semiconductor substrate 1. Then a buried layer 2 which has higher impurity concentration than the layer 4 is partially formed between the substrate 1 and the layer 4. An infrared beam is applied onto the main surface of the substrate 1 and a reflective image 7 obtained by the beam application is used as the reference for mask alignment. After that, impurity is selectively introduced into the surface of the layer 4 by using the mask to form a semiconductor region. With this constitution, even if there is slack or discrepancy in the upper layer, the layer 2 can be recognized directly, and thereby the accuracy of mask alignment for the layer 2 can be improved.

10. 发明专利

JPS644065A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS644065A
公开(公告)日：1989-01-09
申请号：JP15770887
申请日：1987-06-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANAI AKIRA , KAWAMURA MAKOTO , TOCHIKUBO HIROO
IPC分类号： H01L21/76 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To form a transistor of a fine pattern without deteriorating breakdown strength, by forming a selective epitaxial semiconductor region surrounded by sidewalls of SiO2 on one main surface of a semiconductor substrate and then by forming the transistor on a surface of this region and forming a base diffusion layer on a region where lamination defects and facets generated along the sidewalls are avoided. CONSTITUTION:An Si wafer of crystal face (100) is used to perform selective setting of chip bearing so that an orientation flat is made in a slant direction as shown in an arrow. A base diffusion layer 5 is formed by mask diffusion and base/collector junction is formed to be exposed on a surface distant by a fixed length or above from sidewalls 2 made of SiO2. A cause of dielectric strength deterioration is considered to be that base junction is formed on a lamination defect 8 along one sidewall or that a distance between the base diffusion layer 5 and the sidewall 2 s SiO2 is too small. Therefore the base diffusion layer 5 is formed distant by a fixed length (l) from the sidewalls 2. Hence, breakdown strength is prevented from being deteriorated without occurrence of leak through.

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