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1. 发明授权

US3925120A A method for manufacturing a semiconductor device having a buried epitaxial layer 失效
标题翻译：制造具有外延层的半导体器件的方法
公开(公告)号：US3925120A
公开(公告)日：1975-12-09
申请号：US48765974
申请日：1974-07-11
申请人： HITACHI LTD
发明人： SAIDA HIROJI , ONO YUICHI , NOMURA MASAYOSHI , TAMURA MASAO , KOZUKA HIROTSUGU
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8238 , H01L29/00 , H01L29/34 , H01L29/06
CPC分类号： H01L21/823892 , H01L21/74 , H01L21/761 , H01L29/00 , Y10S148/039 , Y10S148/049 , Y10S148/053 , Y10S148/085 , Y10S148/097 , Y10S148/145
摘要： A semiconductor device is formed by providing a p-type semiconductor substrate, a buried n-type epitaxial layer grown in a recess provided on said semiconductor substrate, and an impurity diffused layer provided on a closed band region which is located on the boundary between said semiconductor substrate and said buried epitaxial layer and extends on both sides over both the surfaces of said semiconductor substrate and said buried epitaxial layer. When said semiconductor device is applied to a complementary MOS type integrated circuit, said impurity diffused layer can serve as a channel stopper for a MOS type transistor provided on the buried epitaxial layer.

2. 发明专利

DE3173445D1 MICROWAVE PLASMA ETCHING 未知
公开(公告)号：DE3173445D1
公开(公告)日：1986-02-20
申请号：DE3173445
申请日：1981-09-08
申请人： HITACHI LTD
发明人： NISHIMATSU SHIGERU , SUZUKI KEIZO , NINOMIYA KEN , KANOMATA ICHIRO , OKUDAIRA SADAYUKI , SAIDA HIROJI
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/3213
摘要： A microwave plasma etching system is disclosed which comprises a vacuum chamber for providing a discharge space (5) and provided with an inlet (15) for introducing a discharge gas containing a fluorine-containing gas, magnetic field forming means (7) for forming a magnetic field in the discharge space (5) microwave electric field forming means (3) for forming a microwave electric field in the discharge space (5), and substrate holding means (11) for holding substrates (12) to be processed in the vacuum chamber. To provide freedom from side etching, or control of the degree of side etching, hydrogen is included in the discharge gas. Oxygen may also be included.

3. 发明专利

DE2264126A1 未知
公开(公告)号：DE2264126A1
公开(公告)日：1973-07-19
申请号：DE2264126
申请日：1972-12-29
申请人： HITACHI LTD
发明人： IKEDA TAKAHIDE , SAIDA HIROJI , ISHIKAWA MITIO , NAKAMURA NOBUO
IPC分类号： H01L21/00 , H01L21/265 , H01L23/29 , H01L23/31 , H01L29/00 , H01L29/866 , H01L29/93 , H01G7/00

4. 发明专利

CA1172993A MICROWAVE PLASMA ETCHING 未知
公开(公告)号：CA1172993A
公开(公告)日：1984-08-21
申请号：CA385552
申请日：1981-09-09
申请人： HITACHI LTD
发明人： NISHIMATSU SHIGERU , SUZUKI KEIZO , NINOMIYA KEN , KANOMATA ICHIRO , OKUDAIRA SADAYUKI , SAIDA HIROJI
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/3213 , C23C15/00
摘要： A microwave plasma etching system is disclosed which comprises a vacuum chamber for providing a discharge space and provided with an inlet for introducing a discharge gas containing a fluorine-containing gas, hydrogen and oxygen, magnetic field forming means for forming a magnetic field in the discharge space, microwave electric field forming means for forming a microwave electric field in the discharge space, and substrates holding means for holding substrates to be processed in the vacuum chamber. In the microwave plasma etching, the discharge gas containing fluorine, hydrogen with or without oxygen provides excellent etching almost free from side etching.

5. 发明专利

JPH04150035A SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE USING IT 失效
公开(公告)号：JPH04150035A
公开(公告)日：1992-05-22
申请号：JP27484190
申请日：1990-10-12
申请人： HITACHI LTD
发明人： SAIDA HIROJI , TAKAHASHI KENJI , UMEMURA NOBUAKI , KANAI AKIRA
IPC分类号： H01L29/73 , H01L21/304 , H01L21/322 , H01L21/331 , H01L21/8238 , H01L27/092 , H01L29/732 , H01L29/78
摘要： PURPOSE:To form a semiconductor substrate at a low impurity concentration by a method wherein, when an n-type epitaxial layer is grown, piled-up impurities or a denatured layer are polished and removed down to a prescribed depth by a polishing technique. CONSTITUTION:An n-type epitaxial layer 11 whose impurity concentration is lower than the impurity concentration of an n type semiconductor substrate 10 is grown in a prescribed film thickness on the main face of the substrate 10; partial impurities existing on the surface of the layer 11 or a denatured layer 12 are polished and removed down to a prescribed depth by a polishing technique so that the impurities are not piled up again. Then, an insulating film 5 is formed on the polished surface; a series of processes is executed after that; a transistor is constituted. Thereby, the layer in which the impurities exist in large quantities is removed, the semiconductor substrate can be formed at a low impurity concentration and a MISFET for high breakdown strength can be obtained.

6. 发明专利

JPS62249488A COMPOUND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249488A
公开(公告)日：1987-10-30
申请号：JP9200486
申请日：1986-04-23
申请人： HITACHI LTD
发明人： SAIDA HIROJI , SHIMAZAKI RYUICHI , TOCHIKUBO HIROO , SHIMIZU SHUICHI , KUDO SUMIHISA
IPC分类号： H01L29/812 , H01L21/338 , H01L29/20 , H01L29/80
摘要： PURPOSE:To improve FET characteristics such as mutual conductance by employing an undoped semi-insulating substrate which does not contain impurity for insulation as a semi-insulating substrate. CONSTITUTION:An undoped semi-insulating substrate which is not doped with impurity for insulation such as Cr is employed as a semi-insulatin GaAs substrate 5. This semi-insulating GaAs substrate 5 is formed by a liquid enclosed Czochralski (LEC) method and shows high quality such as low etching pit density. Moreover, a buffer layer 6, an active layer 7 and an ohmic contact layer 7 which are formed on the main surface of the semi-insulating GaAs substrate 5 successively are formed by an organic metal epitaxial growth (MOOCVD) method respectively with uniform quality. Therefore, the thickness of the buffer layer 6 is so selected as to be thicker than the thickness at which the electron mobility in the aotive layer 7 starts declining suddenly and thinner than the thickness at which the leakage current in the buffer layer 6 appears or starts increasing suddenly.

7. 发明专利

JPS59227119A SILICON SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS59227119A
公开(公告)日：1984-12-20
申请号：JP10168183
申请日：1983-06-09
申请人： HITACHI LTD
发明人： SUGASHIRO SHIYOUJIROU , YAMAMOTO NAOKI , NISHIOKA TAIJIYOU , IWATA SEIICHI , OOWADA NOBUO , SAIDA HIROJI
IPC分类号： H01L29/872 , H01L21/28 , H01L21/31 , H01L29/45 , H01L29/47 , H01L29/48
摘要： PURPOSE:To enable the attainment of excellent heat resistance and reliability, by forming a high-melting silicide layer between a transition metal silicide layer and a wiring layer on an Si substrate. CONSTITUTION:A high-melting metal silicide layer 8 composed of WSi2, MoSi2 or the like is formed between a transition metal silicide layer 6 and a wiring layer 5 on an Si semiconductor substrate 1 so as to suppress the interdiffusion of Si and Al between the layers 6 and 5. Since WSi2 or the like is thermally stable in this case, no Si is extricated from the layer 8 and no reaction occurs between the substrate 1 and the layers 6 and 8 and between these layers in heat treatment. Moreover, no reaction occurs between the layers 8 and 5 at a temperature hot higher than 500 deg.C, and in most of methods of manufacturing Si semiconductor devices, heat treatment at a temperature of 500 deg.C or above is not applied practically after wirings are formed. Furthermore, since the melting point of the layer 8 is at 1,300 deg.C or above and the diffusion constant of atoms in the layer 8 is small, the mutual-diffusion of Si in the layer 8 and Al in the layer 5 does not occur.

8. 发明专利

JPS5979550A Manufacture of wiring structure 失效
标题翻译：接线结构的制造
公开(公告)号：JPS5979550A
公开(公告)日：1984-05-08
申请号：JP18904582
申请日：1982-10-29
申请人： Hitachi Ltd
发明人： HINODE KENJI , SAIDA HIROJI
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205
摘要： PURPOSE:To obtain a wiring of high reliability by forming an intermetallic compound in uniform and sufficient thickness containing the side surface of an Al wiring, omitting an etching process and simplifying processes while eliminating problems caused by etching. CONSTITUTION:The Al wiring 3 in approximately 1mum thickness is formed on an Si substrate 1 with an SiO2 film 2, WF6+H2 are mixed into N2 gas, and W4 is applied selectively in the thickness of 300Angstrom . Most of W reacts with Al through treatment at 450 deg.C and an intermetallic compound layer is formed to the surface of the wiring 3, and the corrosion resistance and electromigration resistance of the wiring can be improved. Layer thickness coated hardly depend upon directions because of a CVD method, and the side surface of the wiring, particularly, only an Al surface, can also be coated with the metallic layer in uniform and sufficient thickness. Accordingly, a problem to be caused with the removal of a metal being not reacted can be avoided.
摘要翻译：目的：为了通过形成均匀且足够厚度的包含Al布线的侧面的金属间化合物来获得高可靠性的布线，省略蚀刻工艺并简化工艺，同时消除由蚀刻引起的问题。构成：在具有SiO 2膜2的Si衬底1上形成约1μm厚的Al布线3，将WF 6 + H 2混入N 2气中，选择性地施加厚度为300埃的W4。 W的大部分通过在450℃的处理与Al反应，并且在布线3的表面形成金属间化合物层，能够提高布线的耐腐蚀性和电迁移阻力。由于CVD法，涂层的厚度几乎不依赖于方向，并且布线的侧面，特别是仅Al的表面也可以以均匀且足够的厚度涂覆金属层。因此，可以避免金属脱除未反应而引起的问题。

9. 发明专利

JPS5974622A Electrode of semiconductor device and manufacture thereof 失效
标题翻译：半导体器件的电极及其制造
公开(公告)号：JPS5974622A
公开(公告)日：1984-04-27
申请号：JP18455082
申请日：1982-10-22
申请人： Hitachi Ltd
发明人： KIKUCHI AKIRA , SAIDA HIROJI , MIZUO SHIYOUICHI , KOGIRIMA MASAHIKO
IPC分类号： H01L29/43 , H01L21/28
CPC分类号： H01L21/28
摘要： PURPOSE:To reduce the required area and insure a high reliability as an electrode of a transistor with a shallow emitter depth by forming contacts on a semicondctor substrate with polycrystalline silicon, metal silicide and tangsten. CONSTITUTION:Silicon compound layers 12, 13 on an Si substrate 11 which is to be a base of a transistor are removed by photoetching and an emitter forming part is exposed and polycrystalline Si 14 is selectively deposited only on Si under a prescribed condition. Then an impurity atom such as arsenic is introduced into Si 14 and after an emitter is formed by heat diffusion, palladium, platinum and Ni are deposited and metal silicide 15 is formed by thermal treatment. Then etching of metal is carried out in such a manner that only silicide 15 remains on Si 14 and tangsten 16 is deposited selectively on silicide 15 under a prescribed condition. Finally, Al and Al alloy 17 are deposited on the upper surface and an electrode is formed by photoetching.
摘要翻译：目的：通过在具有多晶硅，金属硅化物和tangsten的半基板上形成接触，减少所需面积并确保具有浅发射极深度的晶体管的电极的高可靠性。构成：通过光刻除去要作为晶体管的基极的Si衬底11上的硅化合物层12,13，并且发射极形成部分被暴露，并且多晶Si 14仅在规定条件下选择性地沉积在Si上。然后将诸如砷的杂质原子引入Si 14中，并且在通过热扩散形成发射体之后，沉积钯，铂和Ni，并通过热处理形成金属硅化物15。然后以这样的方式进行金属蚀刻，使得只有硅化物15保留在Si 14上，并且在规定的条件下选择性地沉积钨16。最后，Al和Al合金17沉积在上表面上，并通过光刻形成电极。

10. 发明专利

JPS5919348A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS5919348A
公开(公告)日：1984-01-31
申请号：JP12752482
申请日：1982-07-23
申请人： Hitachi Ltd
发明人： ISOMAE SEIICHI , TAMURA MASAO , SAIDA HIROJI , KAWAMURA MASAO , AOKI SHIGERU
IPC分类号： H01L21/76 , H01L21/20 , H01L21/762
CPC分类号： H01L21/76202
摘要： PURPOSE:To eliminate a bird beak by forming an insulating film on the desired part of a silicon wafer, selectively growing a silicon crystal on the surface of the silicon except the insulating film forming region, and then partially heating the crystal forming region. CONSTITUTION:A silicon single crystal wafer 2 is oxidized in wet O2 atmosphere of 1,000 deg.C, thereby growing an SiO2 film 4 of approx. 800nm. Then, an SiO2 film is formed by photolithography only on the desired region. Then, SiCl4 gas is flowed at 800 deg.C, and silicon crystal 7 is selectively grown at approx. 700 deg.C only on the region exposed on the silicon surface 6. Then, the crystal 7 is heated partly by the light emitted from a CW argon laser.
摘要翻译：目的：为了通过在硅晶片的所需部分上形成绝缘膜来消除鸟嘴，在除了绝缘膜形成区域之外的硅表面上选择性地生长硅晶体，然后部分地加热晶体形成区域。构成：将硅单晶晶片2在1000℃的湿O2气氛中氧化，从而生长大约2℃的SiO 2膜4。为800nm。然后，仅通过光刻法在所需区域上形成SiO 2膜。然后，SiCl 4气体在800℃流动，硅晶体7选择性地生长在约仅在暴露在硅表面6的区域上。然后，晶体7部分地被从CW氩激光器发射的光部分地加热。

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