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1. 发明专利

JPH0428054A INFORMATION RECORDING/REPRODUCING DEVICE 失效
公开(公告)号：JPH0428054A
公开(公告)日：1992-01-30
申请号：JP13451090
申请日：1990-05-24
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , KAWAMURA TETSUSHI , ARAI SHINICHI , MAEDA TAKESHI , NAGATA SHUNJI
IPC分类号： G11B19/12 , G11B7/00 , G11B7/004 , G11B7/0045 , G11B7/005 , G11B19/02 , G11B19/28
摘要： PURPOSE:To reproduce information on at least two kinds of combination among the combinations of a sport recording system and a width recording system, a CAV system and an MCAV system by providing a reproducing circuit having a function which reproduces a detection signal from a reproducing head with the aid of a method selected by a control circuit. CONSTITUTION:A medium rotation means 22 drives the rotation of a recording medium 26 and the reproducing head 5 detects recorded information from the medium 26. The control circuit 1c is provided with a selecting function which selects the spot recording system or the width recording system based on discrimination information given from the outside or discrimination information detected from the medium 26 and simultaneously selects the CAV system or the MCAV system. The reproducing circuit 1b is provided with the function which reproduces the detection signal from the head 5 by one selected system of the spot recording system and the width recording system and one selected system of the CAV system and the MCAV system. Thus, the information on at least two kinds of combination among the spot recording system and the width recording system, the CAV system and the MCAV system is reproduced.

2. 发明专利

JPH048016A PHASE LOCKED LOOP CIRCUIT AND RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH048016A
公开(公告)日：1992-01-13
申请号：JP11120590
申请日：1990-04-26
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , SUZUMURA SHINTARO , OI FUKASHI , URAGAMI KEN , KARASAWA NORIYUKI , NAGATA SHUNJI , ARAI SHINICHI
IPC分类号： G11B20/10 , G06F1/04 , H03L7/14
摘要： PURPOSE:To prevent malfunction when a data error such as missing of data exists in a data signal by suppressing charge/discharge based on phase comparison in a phase comparator to a loop filter when a data error takes place in the input data signal. CONSTITUTION:When data missing exists, since a reset signal 44 by an edge detection circuit 43 is not generated till a timing when a TR Q232 goes to a high level, a missing detection signal 25 is outputted. The missing detection signal 25 is outputted till the reset signal 44 is generated by a succeeding data. Thus, a gate 23 of a phase locked loop circuit interrupts an INC signal 6 and a DEC signal 7 being outputs of a phase comparator 1 to suppress an INCG signal 26 and a DECG signal 27.

3. 发明专利

JPS6457499A SAMPLE HOLD CIRCUIT 失效
公开(公告)号：JPS6457499A
公开(公告)日：1989-03-03
申请号：JP21282187
申请日：1987-08-28
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： HOTTA MASAO , NAGATA SHUNJI , SHIMIZU TOSHIHIKO , NENE YOSHITO , MAIO KENJI
IPC分类号： G11C27/02 , H03M1/12
摘要： PURPOSE:To obtain a high speed sample hold circuit suitable for a bipolar monolithic IC by disposing a means for switching a diode or a diode connected transistor to a reversely biassing mode. CONSTITUTION:In place of a constant current source, a resistance R1 is used and a circuit for continuously making a current passing through the transistor Q2 connected through the diode to the input transistor Q1 equal to an input signal level is added. The current for generating a voltage drop corresponding to an input voltage flows to the resistance R1 connected as a load, a voltage between the base and the emitter of the transistors Q1, Q2 is substantially constant even when a collector current is changed, and the voltage drop of the resistance R1 follows an input to sample the input signal. In such a way, since the load is the resistance, it is not an obstruction for a high speed like a pnp transistor but the high speed sample hold circuit is obtained.

4. 发明专利

JPH04207321A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPH04207321A
公开(公告)日：1992-07-29
申请号：JP32885990
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , NAGATA SHUNJI , IWAISHI KEISUKE , ISAKA KAZUO
IPC分类号： G11B20/10 , H03L7/14
摘要： PURPOSE:To enable a VCO signal to be synchronized without generating phase fluctuation and step-out for readout data with frequency change and data omission by providing a frequency division means which n-frequency divides an output signal, and a switching means which selects either a frequency division output signal or a non-frequency division output signal. CONSTITUTION:This circuit is comprised of a phase comparator 1, a time difference detection circuit 2, a loop filter 3, a voltage controlled oscillator(VCO) 4, a frequency division circuit 6, and a switching circuit 8. In a phase locking process. the switching means 8 selects a frequency output signal 18, and a phase locking operation is performed. At this time, reference pulse with that becomes the reference of phase comparison and time difference detecting operations is increased compared with a frequency division ratio, and phase difference detecting capacity can be expanded in proportion to the frequency division ratio, therefore, phase locking capacity can be also expanded in proportion to the frequency division ratio. In such a way, it is possible to synchronize the VCO output signal 11 with the readout data signal 10 without generating the phase fluctuation and the step-out for the readout data signal with the frequency change and the data omission.

5. 发明专利

JPH0334158A DATA RECORDER 失效
公开(公告)号：JPH0334158A
公开(公告)日：1991-02-14
申请号：JP16670989
申请日：1989-06-30
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： TATEUCHI TSUGUJI , KOIKE HIDEO , NAGATA SHUNJI , TAKADA YUKITO
IPC分类号： G06F3/06 , G06F12/00 , G11B20/10 , G11B20/12
摘要： PURPOSE:To validate the speediness of a zone bit system by recording a data block on the optimum zone or in the neighborhood of the zone according to attribute data. CONSTITUTION:An address signal conversion part 1 inputs a R/W signal 5, a logic address 6, and the attribute data 7 from an input/output channel 12, and converts the address 6 to a physical address 10 by using a disk working status summary list 13 and a logic address/physical address conversion list 14 stored in a memory 2. The attribute data 7 consists of the priority of a user, a user ID, and a zone No., etc., and supplies a fast zone in sequence of high priority, and that of high priority of an user ID level. Thereby, data can be written on the appropriate zone according to the attribute data, and the optimum arrangement of the data to a fast outer peripheral zone or a slow inner peripheral zone can be easily performed, which validates the speediness of the zone bit system.

6. 发明专利

JPH01305610A VARIABLE GAIN AMPLIFIER 失效
公开(公告)号：JPH01305610A
公开(公告)日：1989-12-08
申请号：JP13552388
申请日：1988-06-03
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： YOSHINO EIJI , NAGATA SHUNJI , TSURUOKA SHUICHI , HIRAI TOMOAKI
IPC分类号： H03G3/02 , H03G3/10
摘要： PURPOSE:To reduce a circuit scale, to decrease energy consumption and to cause a variable gain amplifier suitable for IC formation by providing a current switching circuit to supply a current only to one pair out of plural input transistor pairs. CONSTITUTION:For example, when only a constant current source 1e of a current switching circuit 3 is operated by switching signals S1-Sn, a current I of the constant current source 1e flows through input transistor pairs 1a and 1b as a bias current and only an inputted signal is selected from an input terminal IN1. Then, currents I1 and I2 to correspond to the change of the input signal flow. The currents I1 and I2 are respectively divided by controlling a control voltage terminal VAGC and a reference voltage terminal Vref and currents KI1 and KI2, whose dividing ratio is K, flow to load resistors 12 and 13. Then, an output, whose gain is controlled, is obtained in -Vout and Vout. Thus, an amplifying circuit 2 can be constituted of one step and the reduction of the circuit scale and the reduction of the energy consumption can be realized. Then, the amplifier goes to be optimum for the IC formation.

7. 发明专利

JPS62275292A DUAL PORT COLOR MAPPED DA CONVERTER 失效
公开(公告)号：JPS62275292A
公开(公告)日：1987-11-30
申请号：JP11738286
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： NAGATA SHUNJI , HAYASHI SHINICHI , MAIO KENJI
IPC分类号： H03M1/66 , G09G1/28 , G09G5/06

8. 发明专利

JPH04207322A FREQUENCY SYNTHESIZER 失效
公开(公告)号：JPH04207322A
公开(公告)日：1992-07-29
申请号：JP32887190
申请日：1990-11-30
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SAIKI EISAKU , IWAISHI KEISUKE , NAGATA SHUNJI
IPC分类号： H03L7/187 , H03L7/107
摘要： PURPOSE:To perform fast pull-in by reducing the control voltage of a VCO and to generate an output signal with high accuracy by providing an output means by dividing the output of a frequency phase difference detecting means or that of a charge pump. CONSTITUTION:The optimum loop characteristic can be obtained by setting the output current of a variable output charge pump 14 corresponding to the frequency division ratio of a programmable frequency divider 6 when no phase locking is taken, and a satisfactory pull-in operation can be performed. When the phase locking is taken, the correction cycle of a voltage controlled oscillator(VCO) control voltage 11 can be set at M.T0, and the correction quantity of fluctuation of the VCO control voltage 11 per cycle T1 of a reference signal 7 is set so as to coincide with that by a false correction cycle MT0 per cycle T1. Thereby, it is possible to reduce the fluctuation of the VCO control voltage 11 compared with the VCO control voltage 11 of a frequency synthesizer by conventional technique shown in alternate long and short dash line, and a clock signal 12 with high accuracy can be generated.

9. 发明专利

JPH033166A PHASE SYNCHRONIZING METHOD, PHASE SYNCHRONIZING CIRCUIT, SYSTEM FOR DETECTING DATA SPEED AND SELF-ADVANCING OSCILLATING PERIOD CONTROL MEANS FOR PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH033166A
公开(公告)日：1991-01-09
申请号：JP13602889
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： YOSHINO EIJI , NAGATA SHUNJI , TSURUOKA SHUICHI , MIZOGAMI TAKUYA , SAITO ATSUSHI
IPC分类号： G11B20/10 , H03L7/08 , H04L7/00
摘要： PURPOSE:To surely execute phase synchronization in a shot time even when data to be widely different in data speeds mixedly exist by phase-synchronizing the output of an oscillating circuit controlled in a self-advancing oscillating period specified with the data speed of read data beforehand to a reference signal synchronizing with the read data at the arbitrary data speed. CONSTITUTION:An oscillation permitting signal 13 is generated by the rise of read data 12, and the oscillation is started in a voltage controlled oscillator 5 by the signal. When the portion of one pulse of a reference signal 15 is outputted by such an output 14, the signal 13 is made oscillation-inpermissible by the fall of the pulse, and the oscillator 5 is stopped. Since oscillators 5 and 1 are oscillated by the self-advancing oscillations in the period equal to the ideal oscillating period specified with a data transfer speed according to a control signal 17 beforehand, a reference signal pulse width is equal to a clock signal pulse width T specified from the read data, and it is made equal to the self-advancing oscillating period of the oscillator 10. Thereafter, the phase difference between the reference signal 15 and an oscillating clock signal 22 is detected by a comparator 7, and the advance and lag of the phase are controlled according to it.

10. 发明专利

JPS6390218A DA CONVERTER 失效
公开(公告)号：JPS6390218A
公开(公告)日：1988-04-21
申请号：JP23460986
申请日：1986-10-03
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： NAGATA SHUNJI , MAIO KENJI , HOTTA MASAO , HAYASHI SHINICHI , SHIMIZU TOSHIHIKO
IPC分类号： H03M1/66
摘要： PURPOSE:To cope with both uses for voltage output and current output by providing respective output terminals of the voltage output and the current output. CONSTITUTION:A DA converter which simultaneously generates both of the voltage output and the current output is realized for the purpose of using one integrated DA converter in the voltage output mode as well as the current output mode. That is, a load resistance R2 is incorporated in the integrated circuit of an integrated DA converter 1 having a current output I0 and an output of the inverse of I0 to not only output one current output I0 as a voltage output Vout but also output the other current output of the inverse of I0 as a current output the inverse of Iout as it is, thereby achieving said purpose.

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