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1. 发明专利

JPH11316621A CLOCK SYNCHRONIZING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11316621A
公开(公告)日：1999-11-16
申请号：JP34727298
申请日：1998-12-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA HIROMASA , NAGASHIMA YASUSHI , IDEI YOJI , AOKI MASAKAZU , TANAKA HITOSHI
IPC分类号： G11C11/407 , G06F1/10 , G11C11/4076 , H03K5/13 , H03L7/00
摘要： PROBLEM TO BE SOLVED: To provide a clock circuit which has high accuracy and high responsiveness by constructing a grid-like delay circuit, successively and inputting input clock signals delayed in a 1st signal transmission direction and acquiring the output signals via the output terminals of plural logical means arrayed in the 1st signal transmission direction at the final stage of a 2nd signal transmission direction. SOLUTION: An output pulse CDMout is supplied to a grid-like delay circuit SQUAD1, and the delayed signal of the circuit SQUAD1 is supplied to an edge detection circuit ED2. The circuit ED2 compares the edge of the delayed signal of each stage of the circuit SQUAD1 with the edge of a clock pulse that is delayed more by a single clock and inputted. When both edges match with each other in terms of time, the final stage of the circuit SQUAD1 is detected. Then a multiplexer MPX3 is controlled by a detection signal CNTLB that is produced by the circuit ED2, and an output pulse EDout is outputted from a grid-like delay circuit SQUAD2.

2. 发明专利

JPH11265580A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH11265580A
公开(公告)日：1999-09-28
申请号：JP8492698
申请日：1998-03-16
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KINO KAZUHISA , IDEI YOJI , KITSUKAWA GORO , MISHIMA MICHIHIRO
IPC分类号： G11C11/409 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To shorten a clock cycle period by making memory cycle period roughly identical, lengthening the selection period of column switches, also shortening the precharge period of common complementary input-output lines at the time of reading, shortening the selection period of the column switches and also lengthening the precharge period of the common complementary input- output lines at the time of writing. SOLUTION: This memory chip size is miniaturized by arranging first to fourth subarrays by dividing a subarray SBARY and by allowing 8 lines of subword selection lines FXOB to FB7B to be prolonged so as to penetrate four pairs of the subarrays similarly with a main word line MWL. Since one line of the main word line is provided with respect to the 8 lines of the subword lines on the subarray and the writing pitch of the main word lines MWLs is made to be a lose pitch, it is made easy to form the subword selection lines among the main word lines by utilizing the same wiring layers as those of the main word lines MWLs.

3. 发明专利

JPH10261288A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10261288A
公开(公告)日：1998-09-29
申请号：JP24269596
申请日：1996-08-26
申请人： HITACHI LTD
发明人： NODA HIROMASA , AOKI MASAKAZU , IDEI YOJI
IPC分类号： G06F1/26 , G06F1/10 , G11C11/407 , G11C11/4076 , H01L27/10 , H03K5/13 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To enhance a synchronization accuracy while expanding a synchrinizable clock frequency band by generating pulses whose duties of input pulse width are made small while providing a pulse generating circuit at the input part of a synchronous mirror delay circuit SMD. SOLUTION: A pulse generating circuit constituted of a delay circuit Pw, an inverter N1 and a NAND gate G1 is provided in this device. The delay time in an input part from an buffer B1 to an inverter N3 is made to be the same d1 as that of a buffer circuit B2 and the delay time of inverter circuits N4, N5 is made to be the same d2 as that of a buffer circuit B3 and also these delay times are set in accordance with the delay time of edges of pulses to be transmitted from a forward delay array FDA to a backward delay array BDA via a mirror control circuit MCC and, moreover, the delay time of output circuit inverters N6, N7 is also made to be d2. At this time, the period from an external clock CLKin till an internal clock CLKout just becomes the double period of that of the CLKin .

4. 发明专利

JPH08306184A DYNAMIC TYPE RAM AND MEMORY MODULE, AND ITS REFRESHING METHOD 失效
公开(公告)号：JPH08306184A
公开(公告)日：1996-11-22
申请号：JP24072995
申请日：1995-08-25
申请人： HITACHI LTD
发明人： IDEI YOJI , SHIMOHIGASHI KATSUHIRO , AOKI MASAKAZU , NODA HIROMASA , SATO KATSUYUKI , IWAI HIDETOSHI , SAEKI AKIRA , MURATA JUN , TADAKI YOSHITAKA , SEKIGUCHI TOSHIHIRO , TSUCHIYA OSAMU
IPC分类号： G11C11/406 , G11C11/407
摘要： PURPOSE: To enable refreshing operation which is suitable for an information holding time and has low power consumption by a carrier signal of a refreshing address counter corresponding to a refreshing period made shorter than the shortest information holding time. CONSTITUTION: An address counter generates refreshing address signals A0-A11, and adds it to a programmable-read-only-memory(PROM). The PROM stores a refreshing address signal corresponding to refreshing time setting information of two values whether a refreshing address signal is a signal of refreshing in a short period or a signal of refreshing in a long period. A carrier signal CARRY from an address counter is frequency-divided to 1/m by a (m) value counter, and generates logical product of refreshing time setting information read out from the PROM with an AND gate circuit. Low power consumption can be attained by refreshing inhibiting signals inhibit-0 to inhibit-3 corresponding respectively to an array block 0-3 to an array block-3.

5. 发明专利

JPH0831954A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0831954A
公开(公告)日：1996-02-02
申请号：JP16779294
申请日：1994-07-20
申请人： HITACHI LTD
发明人： YAMAGUCHI KUNIHIKO , IKEDA TAKAHIDE , IDEI YOJI
IPC分类号： H01L21/76 , H01L21/8244 , H01L27/08 , H01L27/11
摘要： PURPOSE:To prevent leak current between first and second element formation regions and to stabilize electrical characteristics by setting the n-type first semiconductor region and n-type second semiconductor region to the same potential. CONSTITUTION:A semiconductor layer 5 is laminated on the main surface of a support substrate 3 via an insulator 4. First and second element formation regions 6A and 6B of the semiconductor layer 5 are mutually separated by a separation groove 11 reaching the insulator 4 from the main surface of the semiconductor layer 5. N-type first semiconductor region 7A and n-type second semiconductor region 7B are formed between n-type well region 8 of the first element formation region 6A of the semiconductor layer 5 and the insulator and between p-type well region 9 of the second element formation region 6B of the semiconductor layer 5 and the insulator 4, respectively. Especially, the n-type first semiconductor region 7A and the n-type second & semiconductor region 7B are set to the same potential, thus preventing leak current between the first element formation region 6A and the second element formation region 6B even if a small defect occurs at the separation groove 11 and the insulator 4.

6. 发明专利

JPH07282579A DRIVING CIRCUIT 失效
公开(公告)号：JPH07282579A
公开(公告)日：1995-10-27
申请号：JP7306094
申请日：1994-04-12
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , KUSUNOKI TAKESHI
IPC分类号： G11C11/407 , H03K19/0175
摘要： PURPOSE:To obtain a sufficient wiring delay reducing effect by connecting drains of transistors of PMOSes and NMOSes with a common output terminal and controlling gate potentials in accordance with an input signal while connecting sources respectively with different power sources. CONSTITUTION:When a signal IN changes now from a low potential to a high potential, a GP1, a GP2 and a GN2 become the high potential and a GN1 becomes the low potential. Consequently, a transistor MN2 conducts and then an output A is lowered to a VSHAfter a time DELTAt, the GN2 changes to the low potential and simultaneously the GN1 changes to the high potential. Consequently, an MN1 conducts in stead of the resistor MN2 and then the A is raised from the VSH to a VSS. On the other hand, when the signal IN changes from the high potential to the low potential, a transistor MP2 conducts for a first DELTAt and then the A is raised to a VCH. Thereafter, a transistor MP1 conducts in stead of the transistor MP2 and then the A is lowered from the VCH to a VCC. Thus, a signal whose amplitude is made large temporarily at the time of a changeover can be obtained.

7. 发明专利

JPH07249981A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH07249981A
公开(公告)日：1995-09-26
申请号：JP3941694
申请日：1994-03-10
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H01L21/822 , H01L27/04 , H03K19/018
摘要： PURPOSE:To prevent the increase of the consumption power by allowing the through current to a CMOS circuit and to prevent the deterioration of the speed of an ECL circuit. CONSTITUTION:The level of a signal OL outputted by an ECL circuit (OLI, OL2,... OEL or the like) is controlled by the power supply voltage VSS of the CMOS circuit driven by the ECL circuit. The level VBB of the input reference potential of the ECL circuit is controlled by the power supply voltage VBB of the CMOS circuit which drives the ECL circuit. Thus, the relative electric potential relation between the L level VLE of the signal to be outputted from the ECL circuit and the power supply voltage VSS of the CMOS circuit can be kept constant so that the NMOS in the CMOS circuit is turned on and the through current passes in the CMOS circuit, resulting in preventing the increase of the consumption power. The relative electric potential relation between the input reference potential VBB of the ECL circuit and the power supply voltage VSS of the CMOS circuit can be almost constant so that the deterioration of the speed of the ECL circuit can be prevented.

8. 发明专利

JPH07231249A DRIVER CIRCUIT 失效
公开(公告)号：JPH07231249A
公开(公告)日：1995-08-29
申请号：JP2087394
申请日：1994-02-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , MASUDA TORU , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H03K17/567 , H03K17/66
摘要： PURPOSE:To reduce power consumption of the driver circuit by connecting a drain of an input transistor(TR) to a collector and a babe of a 1st TR, connecting a collector of a 2nd TR to a base of an output TR and connecting an emitter of the output TR to a collector of a 3rd TR. CONSTITUTION:When an input IN1 is set to an L level, a source-gate voltage of a TR MP1 is higher than a threshold voltage, the TR MP1 is conductive and a current is supplied to an NPN TRQ1. Thus, a current is generated in 2nd and 3rd NPN TRs Q2, Q3 being a current mirror current source. That is, a drive current IC is generated in the TRQ2 and an emitter follower current IEF is generated in the TRQ3. The current IC flows to a resistor R1 to set a base potential of an output NPN TR Q4 to be low and an output terminal being an emitter of the TRQ4 is discharged at a high speed by the current IEF to be set to be low. The currents IC, IEF of the driver circuit are generated when the input is at an L level and not generated when the input is at an H level. Thus, power consumption is reduced.

9. 发明专利

JPH0697747A EMITTER FOLLOWER CIRCUIT 失效
公开(公告)号：JPH0697747A
公开(公告)日：1994-04-08
申请号：JP24295992
申请日：1992-09-11
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , HONMA NORIYUKI , NANBU HIROAKI , IDEI YOJI , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： H03F1/02 , H03F3/50 , H03K19/086
摘要： PURPOSE:To reduce the power consumption of the emitter follower circuit. CONSTITUTION:A drain of a MOS transistor MP of a (p) channel, a base of a pull-down transistor Q2, and one end of a discharge circuit CSW are connected, and on the other hand, a source of the pMOS MP and a collector of the pull-down transistor Q2 are connected to an emitter of an emitter follower transistor Q1. In such a state, a base of the emitter follower transistor Q1 and a gate of the pMOS MP are driven by a signal of the same phase. In such a way, at a transient time when an output OUT is switched from H to L, a large current flows to the pull-down transistor Q2, and at a transient time when its output is switched from L to H, a large current flows to the emitter follower transistor Q1. However, at a steady time of H and L, only a small current flows in both of them. Therefore, the low power consumption is attained.

10. 发明专利

JPH04281290A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04281290A
公开(公告)日：1992-10-06
申请号：JP4352891
申请日：1991-03-08
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/415 , G11C11/407 , H03K19/086
摘要： PURPOSE:To increase the speed of accessing or cycling time by driving a ward line or a data line selecting signal on an ECL circuit. CONSTITUTION:A ward line driver DR of this memory is constituted of a bipolar ECL circuit. Thus, a level conversion circuit for converting the signal of an ECL level into the signal of a BiCMOS level need not be provided between a address buffer constituted of the bipolar ECL circuit and the driver DR and the delaying of an accessing time is prevented as much as delaying time at the level conversion circuit. A data line selecting signal generating circuit is constituted in the same way, as well. Also, a field-effect transistor is preferably used to drive a data line D or to detect a data line signal.

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