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1. 发明专利

JPH0863244A CURRENT SOURCE CIRCUIT 失效
公开(公告)号：JPH0863244A
公开(公告)日：1996-03-08
申请号：JP20073394
申请日：1994-08-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , YAMAZAKI SU , OHATA KENICHI , KUSUNOKI TAKESHI , YAMAGUCHI KUNIHIKO , HIGETA KEIICHI , USAMI MASAMI , ANDO KAZUMASA
IPC分类号： G05F3/22 , H03F3/343
摘要： PURPOSE: To lower the source voltage of the current source circuit which is made small in the temperature dependency and source voltage dependency of a current value. CONSTITUTION: A start-up circuit SU which turns ON when the voltage difference between a source voltage VEE and a ground voltage reaches a specific voltage to supply a current and reaches high impedance when transistors(TR) Q2 and Q3 turn ON as a result and then TRs Q1 and QCS turn ON is connected to the bases of the Q2 and Q3. A current source I1 uses a current which flows when the Q2 turns ON. One end of a resistance RE is connected directly to the VEE and the other end is connected to the ground voltage through a high- impedance circuit (QCS, Q3, and I1) and also connected to the VEE thorugh a low-impedance circuit (QCS, Q3, Q2, R2, and Q1). The ratio of emitter current density of the Q1, Q2, Q3, and QCS is set to 1:1:1/20:1.

2. 发明专利

JPH07161844A MEMORY CELL AND MEMORY DEVICE 失效
公开(公告)号：JPH07161844A
公开(公告)日：1995-06-23
申请号：JP31154593
申请日：1993-12-13
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： IDEI YOJI , NANBU HIROAKI , KANETANI KAZUO , MASUDA TORU , YAMAGUCHI KUNIHIKO , OHATA KENICHI , KUSUNOKI TAKESHI
IPC分类号： G11C11/41 , G11C11/412 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To realize a static memory cell having high resistance to soft error generated by alpha ray. CONSTITUTION:A memory cell 200 has a coupling capacitor Cc between two information storage nodes 1, 2. A p well (or p substrate), in which drive MOS transistors Mn5 and Mn4 and transfer MOS transistors Mn1 and Mn2 are formed, is connected to a Vbb generating circuit 210. The voltage Vbb is set lower than a low level VL of a signal potential of the memory cell. This causes a parasitic diode between the sources of MN1. to MN4 or a n type diffusion layer corresponding to a drain and the p well (or p substrate) not to be ON even when a potential fluctuation DELTAVL of the node 2 on the low potential side is large, thus preventing mal function.

3. 发明专利

JPH04254992A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04254992A
公开(公告)日：1992-09-10
申请号：JP1443291
申请日：1991-02-05
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , SAKURAI YOSHIAKI
IPC分类号： G11C11/413 , G11C11/417
摘要： PURPOSE:To obtain a level transforming circuit on which an operating speed is not reduced even under a low power source voltage required for the lower breakdown strength of elements caused by making fine elements such as transistors and resistors. CONSTITUTION:The amplifier circuit of the level transforming circuit is composed of bipolar transistors; the level transforming circuit consists of the amplifier circuit AMP composed of pnp transistor QDP and npn transistor QDN whose collectors are connected to an output terminal Vout, bias circuits BP, BN with which each base of the above transistors are biased, and a signal transmission circuit STC through which the AC component and the DC component of inputted signals are transmitted to the above amplifier circuit AMP.

4. 发明专利

JPH0427000A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0427000A
公开(公告)日：1992-01-30
申请号：JP12921890
申请日：1990-05-21
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , IDEI YOJI , SAKURAI YOSHIAKI
IPC分类号： G11C29/00 , G11C29/06
摘要： PURPOSE:To easily execute a screening test by providing a switch separating an internal power supply voltage generating circuit and a memory cell to the circuit for the semiconductor memory. CONSTITUTION:A control signal TE is at a high potential at the screening test. Thus, a 1st switch comprising MOS transistors (TRs) MN101, MP101 and a 2nd switch comprising MOS TRs MN102, MP102 are nonconductive and a 3rd switch comprising MOS TR MN103 is conductive. Thus, a low potential power terminal of a word line W and memory cells MC1, MC2 are connected to an external power supply VEXT1 for the screening test and the potential of the VEXT1 is decreased more than a voltage of a VB to apply a high voltage to the memory cells MC1, MC2. Thus, the screening test is easily executed.

5. 发明专利

JPH0362615A SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0362615A
公开(公告)日：1991-03-18
申请号：JP19658889
申请日：1989-07-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/414 , H03K19/086
摘要： PURPOSE:To decrease the fluctuation of a current due to process fluctuation by providing a 1st current mirror circuit and a 2nd current mirror circuit each comprising a transistor(TR) whose emitter is connected to a constant voltage source and a diode. CONSTITUTION:TRs Q3, Q7 and Q4 and Q8 form respectively current mirror circuits. Moreover, the collector current of a TR Q1 is equal to the collector current or the TR Q3 because the TR Q1 and a diode D1 form a current mirror circuit when the junction area of the TR Q1 and the diode D1 is equal to each other. Then the TRs Q7, Q3 are formed the same structure, and only the base- emitter junction area of the TR Q3 is made twice that of the TR Q7 or the TRs Q3, Q7 are formed to the same structure and same size, and 2 TRs Q3 are connected in parallel. Thus, even when the TR characteristic is changed due to process variance, the collector current of the TR Q3 is constant and the collector current of the TR Q1 is unchanged, then the fluctuation of the current due to process variance is reduced.

6. 发明专利

JPH0362396A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0362396A
公开(公告)日：1991-03-18
申请号：JP19658789
申请日：1989-07-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , NANBU HIROAKI , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/413
摘要： PURPOSE:To quicken the access time by adopting the constitution such that a bit line drive current branched to a bypass circuit does not flow to a sense circuit and controlling a base level of a bypass transistor (TR) driving a bit line. CONSTITUTION:When a word line W1 and a bit line selection signal line Y1 are selected, for example at readout state and a TR QM0 of a memory cell M11 is turned on, a TR QC10 of a bypass circuit BNKP1 is turned on and a base level of a TR QPB11 is decreased. As a result, a bit line drive current IRO partly flows to the cell M11 and partly flows to the TR QBP10 but does not flow to a sense line SL0. On the other hand, a bit line drive current IR1 entirely flows to a sense line SL1 through a read write control TR QR11. Since a current difference flowing to the sense lines SL0 and SL1 required for the sense operation is large, the sense circuit SA is operated at a high speed.

7. 发明专利

JPH033194A BIPOLAR MEMORY 失效
公开(公告)号：JPH033194A
公开(公告)日：1991-01-09
申请号：JP13604589
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： IDE YOJI , OHATA KENICHI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , NANBU HIROAKI , SAKURAI YOSHIAKI
IPC分类号： G11C11/414
摘要： PURPOSE:To obtain a bipolar memory which has a large capacity and, simultaneously, in which read/write are high-speed by directly driving a digit line with the emitter of a digit line driving transistor. CONSTITUTION:A pair of digit lines DL11 and L12 are directly driven by the emitters of digit line driving transistors Q11 and Q12 without the intervention of a resistance. In such a way, since the charge of a digit line load capacity is directly xecuted with a bipolar transistor in which a current driving ability is high, a very high speed is obtained, and consequently, even when the parasitic capacities of the digit lines DL11 and DL12 are large, the potential can be raised at a high speed. The current to flow to the collectors of the driving transistors Q11 and Q12 of the selected pair of digit lines DL11 and DL12 is different for information stored in the memory call to be selected, thereby, the information can be read by sensing the current difference.

8. 发明专利

JPH02265093A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02265093A
公开(公告)日：1990-10-29
申请号：JP8486489
申请日：1989-04-05
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/41 , G11C11/412 , G11C11/414
摘要： PURPOSE:To shorten the charge/discharge time of a bit line without increasing the power consumption by providing a means for supplying a current IR to only a pair of bit lines which are selected, or a means for supplying transiently the current IR to only a pair of bit lines switched to a selection and setting as IR > cell current ICELL. CONSTITUTION:A word line W1 turns on an SW1 and turns off an SW2 at the time t0 of a selective level, and by switching selected bit lines from BL2, BR2 to BL1, BR1, a cell MC11 is read out. In this case, currents of the bit lines BL1, BR1 are (ICELL+IB), IB before t0, and usually (ICELL+IB)

9. 发明专利

JPH02264878A METHOD FOR MEASURING ACCESS TIME 失效
公开(公告)号：JPH02264878A
公开(公告)日：1990-10-29
申请号：JP8486289
申请日：1989-04-05
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G01R31/28 , G11C29/00 , G11C29/56 , G01R31/318
摘要： PURPOSE:To enable highly-precise measurement of an access time with ease by connecting each memory to a memory adjacent thereto and by measuring a delay time between an input signal to the first memory and an output signal from the last memory. CONSTITUTION:An access time of RAM (Random Access Memory) is measured. When the number of RAMs is assumed to be three, on the occasion, data output terminals DO of RAMs 1 and 2 are connected to address input terminals AO of RAMs 2 and 3 respectively. The terminal AO and a data input terminal DI are connected through an inverter in each RAM, while a terminal WEO is provided and each write-in control terminal WE is connected thereto commonly. A delay time between a signal inputted to the terminal AO of the RAM 1 and a signal outputted from the terminal DO of the RAM 3 is measured and an average access time is determined.

10. 发明专利

JPH02232897A SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH02232897A
公开(公告)日：1990-09-14
申请号：JP5188889
申请日：1989-03-06
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , HONMA NORIYUKI , YAMAGUCHI KUNIHIKO , KANETANI KAZUO , IDEI YOJI , OHATA KENICHI , SAKURAI YOSHIAKI
IPC分类号： G11C11/411 , H01L27/10
摘要： PURPOSE:To obtain a memory, which can execute an access at high speed, by providing first and second transistors, whose bases are respectively connected to first and second nodes of an FF, and a third transistor, of which a base is connected to a word line and an emitter is connected to a bit line, in a memory cell composed of the FF. CONSTITUTION:The FF composed of bipolar transistors QC1 and QC2 is defined as the basic constitution of the memory cell and the bases of transistors Q1 and Q2 are respectively connected to the bases of the QC1 and QC2. Then, the collector of a transistor Q3 is commonly connected to the emitters of the Q1 and Q2 and the base is connected to a word line W2. Afterwards, the emitter is connected to a bit line IR and the memory cell is constituted. At the time of reading, when a reading current is supplied to the bit line IR, the Q3 to be connected to the bit line IR constitutes one current switch. The switching voltage, namely, the voltage amplitude of a base input for the Q can be 0.4V at maximum and the potential of the bit line IR is lower than that of a word line W2 only by VBE. The relation is established concerning other plural bit lines IWL and IWR. Namely, the potentials of all the bit lines are made equal and the voltage amplitude is O. Then, the charging and discharging time of the word line and bit line can be made small.

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