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    • 4. 发明专利
    • Protection circuit
    • 保护电路
    • JP2009267072A
    • 2009-11-12
    • JP2008114771
    • 2008-04-25
    • Hitachi Ltd株式会社日立製作所
    • SHINOMIYA TOSHIOYOKOYAMA YUJIHASE AKIHIROKITA MASAHITO
    • H01L21/822H01L27/04H01L27/06
    • H02H9/046
    • PROBLEM TO BE SOLVED: To provide a protection circuit for protecting a semiconductor integrated circuit device from an electrostatic breakdown or a latch-up which may be caused by applying a high voltage between power supplies by external surge or the like when device destruction resistance is reduced due to the microfabrication of a process or voltage reduction.
      SOLUTION: A drain terminal of a PMOS transistor MP1 having a source terminal connected to a power supply VDD and having a gate terminal connected to a control signal VG1 generated from the control circuit 2 on the basis of a power supply GND is connected to one end of a resistor R1 having the other end connected to the power supply GND and to a gate terminal of an NMOS transistor MN1 having a drain terminal and a source terminal which are respectively connected to the power supply VDD and the power supply GND, as an internal signal VG2. When an optional voltage and more is applied between the power supplies, the power supply is short-circuited with the other.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种用于保护半导体集成电路器件免受静电击穿或闩锁的保护电路,这可能是由于当器件破坏时通过外部浪涌等在电源之间施加高电压而引起的 由于过程的微细加工或电压降低,电阻降低。 解决方案:连接到电源VDD并且具有连接到基于电源GND从控制电路2产生的控制信号VG1的栅极端子的源极端子的PMOS晶体管MP1的漏极端子被连接 到另一端连接到电源GND的电阻器R1的一端和具有分别连接到电源VDD和电源GND的漏极端子和源极端子的NMOS晶体管MN1的栅极端子, 作为内部信号VG2。 当在电源之间施加可选的电压和更多电压时,电源与另一个电源短路。 版权所有(C)2010,JPO&INPIT
    • 7. 发明专利
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • JP2000349617A
    • 2000-12-15
    • JP15724699
    • 1999-06-04
    • HITACHI LTD
    • OKAZAKI TAKAOHASE AKIHIRO
    • H03K19/0185
    • PROBLEM TO BE SOLVED: To stably convert a level of an input signal having a low power supply voltage amplitude into a level of a signal with a high power supply voltage amplitude while reducing the power consumption and the area of a level conversion circuit. SOLUTION: When a signal at a low level is given to a level conversion circuit 1, transistors(TRs) 12, 9 are respectively turned on and off, a node (e) reaches a high level and a TR 4 is turned off. Since a node (d) is at a low level, an output of a node (f) goes to a low level. When a signal at a high level (a breakdown voltage VDL) is given to the level conversion circuit 1, the TRs 12, 9 are respectively turned on and off. The node (e) goes to a low level, the TR 4 is turned on, the node (d) approaches a high level and the node (e) goes to a low level. The TR 4 carries more current so that the node (d) becomes at a high level and a high level signal (power supply voltage Vcc) receiving level conversion is outputted to the node (f).