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    • 1. 发明专利
    • Protection circuit
    • 保护电路
    • JP2009267072A
    • 2009-11-12
    • JP2008114771
    • 2008-04-25
    • Hitachi Ltd株式会社日立製作所
    • SHINOMIYA TOSHIOYOKOYAMA YUJIHASE AKIHIROKITA MASAHITO
    • H01L21/822H01L27/04H01L27/06
    • H02H9/046
    • PROBLEM TO BE SOLVED: To provide a protection circuit for protecting a semiconductor integrated circuit device from an electrostatic breakdown or a latch-up which may be caused by applying a high voltage between power supplies by external surge or the like when device destruction resistance is reduced due to the microfabrication of a process or voltage reduction.
      SOLUTION: A drain terminal of a PMOS transistor MP1 having a source terminal connected to a power supply VDD and having a gate terminal connected to a control signal VG1 generated from the control circuit 2 on the basis of a power supply GND is connected to one end of a resistor R1 having the other end connected to the power supply GND and to a gate terminal of an NMOS transistor MN1 having a drain terminal and a source terminal which are respectively connected to the power supply VDD and the power supply GND, as an internal signal VG2. When an optional voltage and more is applied between the power supplies, the power supply is short-circuited with the other.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种用于保护半导体集成电路器件免受静电击穿或闩锁的保护电路,这可能是由于当器件破坏时通过外部浪涌等在电源之间施加高电压而引起的 由于过程的微细加工或电压降低,电阻降低。 解决方案:连接到电源VDD并且具有连接到基于电源GND从控制电路2产生的控制信号VG1的栅极端子的源极端子的PMOS晶体管MP1的漏极端子被连接 到另一端连接到电源GND的电阻器R1的一端和具有分别连接到电源VDD和电源GND的漏极端子和源极端子的NMOS晶体管MN1的栅极端子, 作为内部信号VG2。 当在电源之间施加可选的电压和更多电压时,电源与另一个电源短路。 版权所有(C)2010,JPO&INPIT
    • 2. 发明专利
    • Switch circuit and semiconductor circuit
    • 开关电路和半导体电路
    • JP2012209763A
    • 2012-10-25
    • JP2011073891
    • 2011-03-30
    • Hitachi Ltd株式会社日立製作所
    • SHIMIZU TETSUHIROHANAZAWA SATOSHISHINOMIYA TOSHIOYOSHIZAWA HIROYASU
    • H03K17/693A61B8/00H03K17/16
    • H03K17/6874G01S7/52017
    • PROBLEM TO BE SOLVED: To provide a T/R switch circuit that, when applied to an ultrasonograph or the like, transmits a low-noise wideband signal reflected from a living body to a reception circuit while preventing malfunctions of a switch due to potential fluctuations in transmitted or reflected signals, and damage to elements.SOLUTION: The switch circuit includes: a two-way switch circuit in which sources of two MOS transistors are connected together in series into a common source terminal, gate terminals of the two-way switch circuit are connected together into a common gate terminal, and drains of the two MOS transistors are connected to input/output terminals; and a floating gate voltage control circuit that is connected to the common gate terminal and the common source terminal, makes a potential at the common gate terminal follow in phase in accordance with fluctuations in a potential at the common source terminal, and feeds a signal to turn the switch on or off to the common gate terminal.
    • 要解决的问题:提供一种T / R开关电路,当应用于超声波仪等时,将从活体反射的低噪声宽带信号发送到接收电路,同时防止开关故障 传输或反射信号的潜在波动,以及元素的损坏。 解决方案:开关电路包括:双向开关电路,其中两个MOS晶体管的源极串联连接成公共源极,双向开关电路的栅极端子连接在一起,形成公共栅极 端子和两个MOS晶体管的漏极连接到输入/输出端子; 以及连接到公共栅极端子和公共源极端子的浮置栅极电压控制电路,根据公共源极端子的电位的波动,在公共栅极端子处使电位相位相同,并且将信号馈送到 将开关打开或关闭到公共端子。 版权所有(C)2013,JPO&INPIT
    • 3. 发明专利
    • Semiconductor integrated circuit device
    • 半导体集成电路设备
    • JP2009253779A
    • 2009-10-29
    • JP2008100946
    • 2008-04-09
    • Hitachi Ltd株式会社日立製作所
    • SHINOMIYA TOSHIOKOYAMA AKIOYOKOYAMA YUJI
    • H03K17/22
    • H03K17/223G06F1/24
    • PROBLEM TO BE SOLVED: To solve the problem of a semiconductor integrated circuit device for generating an internal power supply from an external power supply, with a risk of causing unstable operation due to an unfixed state of a control signal when the external power supply is applied, and the internal power supply starts up. SOLUTION: The semiconductor integrated circuit device includes an internal power supply generating circuit 1, a control circuit 3 for supplying a first control signal D1 by supplying the internal power supply VDD to it, and a power reset circuit 2 to generate a reset signal RST when the internal power supply starts up, and when the internal power supply starts up, the reset signal masks the unfixed state of the first control signal supplied from the control circuit. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了解决用于从外部电源产生内部电源的半导体集成电路装置的问题,具有当外部电源时由于控制信号的未固定状态引起的不稳定操作的风险 供电,内部电源启动。 解决方案:半导体集成电路器件包括内部电源产生电路1,用于通过向其提供内部电源VDD来提供第一控制信号D1的控制电路3和用于产生复位的电源复位电路2 当内部电源启动时产生信号RST,当内部电源启动时,复位信号屏蔽从控制电路提供的第一控制信号的未固定状态。 版权所有(C)2010,JPO&INPIT
    • 4. 发明专利
    • Reproduction circuit and magnetic disk device using the same
    • 再现电路和使用该磁盘的磁条设备
    • JP2007149274A
    • 2007-06-14
    • JP2005344879
    • 2005-11-30
    • Hitachi Ltd株式会社日立製作所
    • YOSHIZAWA HIROYASUKOBAYASHI YOICHIROSHINOMIYA TOSHIO
    • G11B5/09
    • G11B5/02G11B2005/0018
    • PROBLEM TO BE SOLVED: To provide a reproduction circuit for a magnetic disk device for stably shifting a write mode to a read mode at high speed.
      SOLUTION: The reproduction circuit for the magnetic disk device comprising a bias circuit 200 for giving a bias voltage to an MR (magneto-resistance effect type) head 100, an amplifier circuit 300 for amplifying the output of the MR head 100, capacitances C0 and C1 for cutting DC components of the output of the MR head 100, and a conductor amplifier 400 for giving the input bias of the amplifier 300 is further provided with a switch SO for short circuit for charging the DC cut capacitances C0 and C1. When performing mode shift from write to read, a mode shift characteristic that attains both high speed property and stability is obtained by turning the short circuit switch SO on and charging the DC cut capacitances C0 and C1.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种用于将写入模式稳定地转换为读取模式的磁盘装置的再现电路。 解决方案:用于磁盘装置的再现电路包括用于向MR(磁阻效应型)头100提供偏置电压的偏置电路200,用于放大MR磁头100的输出的放大器电路300, 用于切割MR头100的输出的DC分量的电容C0和C1以及用于给出放大器300的输入偏置的导体放大器400还设置有用于对DC切断电容C0和C1进行充电的用于短路的开关SO 。 当从写入读取进行模式切换时,通过使短路开关SO接通并对直流切断电容C0和C1进行充电来获得实现高速性能和稳定性的模式移位特性。 版权所有(C)2007,JPO&INPIT
    • 5. 发明专利
    • Semiconductor integrated circuit device
    • 半导体集成电路设备
    • JP2010193329A
    • 2010-09-02
    • JP2009037338
    • 2009-02-20
    • Hitachi Ltd株式会社日立製作所
    • HANAZAWA SATOSHISHINOMIYA TOSHIOYOSHIZAWA HIROYASU
    • H03K17/687
    • H03K17/74H03K17/6874
    • PROBLEM TO BE SOLVED: To provide such a circuit configuration that an output is bot brought into a high impedance state in order to improve erroneous transmission or a waveform over shoot in a transmission circuit in which a vibrator is driven by a voltage pulse, and to provide a semiconductor integrated circuit device in which a plurality of channels are integrated.
      SOLUTION: A transmission circuit comprises a conventional pulse generating circuit 10 to which a positive voltage VPP1 and a negative voltage VNN1 of the first highest absolute value are supplied; a P-type analog switch type pulse generating circuit 20 to which a positive voltage VPP2 of the second highest absolute value is supplied; an N-type analog switch type pulse generating circuit 30 to which a negative voltage VNN2 of the second highest absolute value is supplied; and an N-type analog switch type ground level damping circuit 40 to which ground potential is supplied. In such a transmission circuit, the circuits 10, 20, 30 and 40 are connected to an output terminal OUT, respectively. The circuits 10, 20, 30 and 40 are turned on and off, respectively, according to switch control signals S1-S5, thereby driving an ultrasonic vibrator 50.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:为了提供这样的电路结构,即输出机器人进入高阻抗状态,以便改善传输电路中的错误传输或波形,其中振动器由电压脉冲驱动 并且提供其中集成了多个通道的半导体集成电路器件。 解决方案:传输电路包括常规脉冲发生电路10,其中提供正电压VPP1和第一最高绝对值的负电压VNN1; 提供第二高绝对值的正电压VPP2的P型模拟开关型脉冲发生电路20; 提供第二高绝对值的负电压VNN2的N型模拟开关型脉冲发生电路30; 以及提供接地电位的N型模拟开关型接地电平阻尼电路40。 在这种传输电路中,电路10,20,30和40分别连接到输出端OUT。 电路10,20,30,40根据开关控制信号S1-S5分别导通和截止,从而驱动超声波振动器50.(C)2010,JPO&INPIT
    • 6. 发明专利
    • Reproduction circuit and magnetic disk device using the same
    • 再现电路和使用该磁盘的磁条设备
    • JP2007265582A
    • 2007-10-11
    • JP2006092778
    • 2006-03-30
    • Hitachi Ltd株式会社日立製作所
    • SHINOMIYA TOSHIOKOBAYASHI YOICHIRONOMURA YOSHIKI
    • G11B5/02
    • G11B5/40G11B2005/0016
    • PROBLEM TO BE SOLVED: To provide a magnetic disk reproduction circuit, wherein when the abnormal fluctuation in power supply voltage including power ON/OFF occurs, an MR head bias is prevented from exceeding a prescribed value, and the center potential of the MR head is controlled to a ground.
      SOLUTION: The reproduction circuit for the magnetic disk device is provided with an MR head, a bias circuit for applying a prescribed bias voltage to the MR head, an amplifier circuit for amplifying the output signal of the MR head, a power supply voltage monitoring circuit for monitoring power supply voltage fluctuation, and a control circuit controlled by the power supply voltage monitoring circuit. When the abnormal fluctuation in power supply voltage including power ON/OFF occurs, the MR head bias voltage is prevented from exceeding a prescribed value by the control circuit, and the center potential of the MR head is controlled to protect the MR head.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供一种磁盘再现电路,其中当发生包括电源ON / OFF的电源电压的异常波动时,防止MR磁头偏置超过规定值,并且, MR头被控制到地面。 解决方案:磁盘装置的再现电路设置有MR磁头,用于向MR磁头施加规定的偏置电压的偏置电路,用于放大MR磁头的输出信号的放大电路,电源 用于监视电源电压波动的电压监控电路,以及由电源电压监控电路控制的控制电路。 当发生包括电源ON / OFF的电源电压的异常波动时,通过控制电路防止MR头偏置电压超过规定值,并且控制MR磁头的中心电位以保护MR磁头。 版权所有(C)2008,JPO&INPIT
    • 9. 发明专利
    • MAGNETIC DISC MEMORY DEVICE
    • JP2001023107A
    • 2001-01-26
    • JP19684199
    • 1999-07-12
    • HITACHI LTD
    • HIROSE TAKESHISHINOMIYA TOSHIO
    • G11B5/82G11B5/02G11B19/02
    • PROBLEM TO BE SOLVED: To obtain a magnetic disc memory device which can obtain a wide band read signal amplitude with a simple construction. SOLUTION: A read amplifier, which gives a ground potential to a magnetic disc and operates with positive and negative potentials with the ground potential as a neutral, and comprises a 1st stage amplifier 1stAMP which amplifies the read signal of a magneto-resistance head which reads recorded information from a recording surface and a next stage amplifier 2ndAMP which receives the amplified signal, is provided. The next stage amplifier 2ndAMP comprises 1st and 2nd amplification transistors which receive the amplified signals with phases opposite to each other from the 1st stage amplifier 1stAMP via their respective bases, 1st and 2nd load resistors provided between the respective collectors of the amplification transistors and a 1st voltage, 1st and 2nd emitter resistors RE connected to the respective emitters of the amplification transistors, a current source circuit provided between the other end of the common connection of the emitter resistors and the 1st voltage, 3rd and 4th load resistors whose one side ends are connected to the collectors of the 1st and 2nd amplification transistors, and a switching device which are provided between the other side ends of the load resistors and whose switching is controlled by a gain changing signal.