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    • 3. 发明专利
    • MANUFACTURE OF ELECTRONIC PART
    • JPH09269294A
    • 1997-10-14
    • JP8020096
    • 1996-04-02
    • HITACHI LTDHITACHI ELECTR ENG
    • SHIBA MASATAKAWATANABE KENJIHAMADA TOSHIMITSUISHIKAWA SEIJIGO NAOKIYANAI TOSHIAKIWATANABE TETSUYAJINGU TAKAHIRO
    • G01N21/84B23Q41/08G05B19/418G06Q50/00G06Q50/04H01L21/66
    • PROBLEM TO BE SOLVED: To establish an optimum examination device and a frequency of examination in manufacture of semiconductor wafers and the like. SOLUTION: Each examination device of a group 1 of examination devices is connected to a network 8, and after an examination is finished, the result is transferred to a data gathering system 2. Where a predetermined badness mode is confirmed, same waferes selected from a predetermined process are examined by examination devices of different type of the group of examinations devices 1 and the data are gathered and analyzed to calculate the degree of correlation between types of device 4. On the other hand, a mean frequency of occurrence of badness may be obtained by analyzing the badness occurrence progress in the same process 5. Then, an optimum examination device and a frequency of examination are successively obtained on the basis of the results of calculations of calculation processing of the degree of correlation between types of device and of calculation processing of frequency of occurrence of badness 6, and the method of introduction of wafers into the group of examination devices 1 or the like is indicated through a system 7 managing the group of examination devices. It is thus possible to easily establish complicated conditions of examination such as an applied examination device, a frequency of examination and the like in manufacture of electronic parts as well as dramatically improve the economic efficiency of examination by performing an expected value minimization of the overall loss.