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    • 7. 发明专利
    • MANUFACTURE OF ELECTRONIC PART
    • JPH09269294A
    • 1997-10-14
    • JP8020096
    • 1996-04-02
    • HITACHI LTDHITACHI ELECTR ENG
    • SHIBA MASATAKAWATANABE KENJIHAMADA TOSHIMITSUISHIKAWA SEIJIGO NAOKIYANAI TOSHIAKIWATANABE TETSUYAJINGU TAKAHIRO
    • G01N21/84B23Q41/08G05B19/418G06Q50/00G06Q50/04H01L21/66
    • PROBLEM TO BE SOLVED: To establish an optimum examination device and a frequency of examination in manufacture of semiconductor wafers and the like. SOLUTION: Each examination device of a group 1 of examination devices is connected to a network 8, and after an examination is finished, the result is transferred to a data gathering system 2. Where a predetermined badness mode is confirmed, same waferes selected from a predetermined process are examined by examination devices of different type of the group of examinations devices 1 and the data are gathered and analyzed to calculate the degree of correlation between types of device 4. On the other hand, a mean frequency of occurrence of badness may be obtained by analyzing the badness occurrence progress in the same process 5. Then, an optimum examination device and a frequency of examination are successively obtained on the basis of the results of calculations of calculation processing of the degree of correlation between types of device and of calculation processing of frequency of occurrence of badness 6, and the method of introduction of wafers into the group of examination devices 1 or the like is indicated through a system 7 managing the group of examination devices. It is thus possible to easily establish complicated conditions of examination such as an applied examination device, a frequency of examination and the like in manufacture of electronic parts as well as dramatically improve the economic efficiency of examination by performing an expected value minimization of the overall loss.
    • 10. 发明专利
    • ERASING METHOD FOR ELIMINATED AREA OF IC CHIP
    • JPH0621179A
    • 1994-01-28
    • JP22883691
    • 1991-08-14
    • HITACHI ELECTR ENG
    • JINGU TAKAHIRO
    • G01N21/88G01N21/94G01N21/956H01L21/66H01S3/00
    • PURPOSE:To provide a method wherein a part of the IC chip where a reflectance is abnormally large is determined to be an eliminated area and the position of the part is specified and an elimination threshold which eliminates the picture element signal of that part is obtained and the respective IC chips are tested successively this way and the map display of the removed areas is erased in a foreign substance inspection employing an adjacent chip comparing method. CONSTITUTION:One of chip rows in a wafer is arbitrarily selected as a test chip row and the test chip row is scanned by a laser beam LX to obtain the respective differential data Q of respective adjacent chips (A, B), (B, C),... successively. The absolute values of the picture element signals of the respective differential data corresponding to the identical positions of the respective chips are successively added by an adding circuit 5a and stored in the respective picture element memories of a map memory 5. The data among the stored added data SIGMA¦Q¦ which are larger than a certain value are determined as elimination thresholds VD for eliminated areas and the thresholds and the addresses (i, j) of the eliminated areas in the map memory are stored by a RAM 5c.