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1. 发明专利

JPH10256512A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10256512A
公开(公告)日：1998-09-25
申请号：JP10223198
申请日：1998-03-30
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize a high-capacity semiconductor device by placing first to fourth decoder circuits along connections of first regions and first to fourth memory arrays and fifth to eighth decoder circuits along connections of second regions and first to fourth memory arrays. SOLUTION: Memory arrays are disposed at four divided areas of a cross area composed of the longitudinal and transverse center zones of a chip; areas A and B are at the left and right of the transverse center zone, areas C and D are the upper and lower parts of the longitudinal center zone, and area E is at the cross section of both zones. Decoders and drivers for selecting the memory arrays are disposed at the periphery of the area A adjacent to the arrays, and bonding pads are disposed at the longitudinal center areas.

2. 发明专利

GB2151846A A high voltage destruction-prevention circuit for a semiconductor integrated circuit device 未知
公开(公告)号：GB2151846A
公开(公告)日：1985-07-24
申请号：GB8431596
申请日：1984-12-14
申请人： HITACHI LTD
发明人： YAMAGUCHI YASUNORI , SAWADA JIRO
IPC分类号： G11C11/413 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/76 , H01L23/56 , H01L27/04
摘要： An IC is provided with high voltage destruction-preventing circuit (7) which consists of a resistor (R1) and a bipolar lateral transistor (Tr). A first semiconductor region constitutes the resistor (R1), and a second semiconductor region of the same conductivity type as the first semiconductor region is spaced at a predetermined distance from the first semiconductor region. Thus, a parasitic, lateral transistor (Tr) made up of the semiconductor substrate and first and second semiconductor regions is formed. In addition, the length of opposed edges of the first and second semiconductor regions can be set substantially equal to or not less than the channel width of a clamping MISFET (Q2) so as to reduce rapidly and reliably an unexpected, excessively high voltage which could cause destruction of the input circuit. The second semiconductor region may be part of a guard ring or other structure carrying a suitable bias voltage thus reducing the additional space required for the protective circuit.

3. 发明专利

JPH07220497A SEMICONDUCTOR DEVICE AND TEST METHOD THEREFOR 失效
公开(公告)号：JPH07220497A
公开(公告)日：1995-08-18
申请号：JP1198194
申请日：1994-02-03
申请人： HITACHI LTD
发明人： SAWADA JIRO
IPC分类号： G06F12/16 , G11C11/401 , G11C29/00 , G11C29/34
摘要： PURPOSE:To distinguish the information of a required cell in a short time by delivering information of one bit unit to a parallel test function at high rate. CONSTITUTION:A selection is made among a parallel test mode a binary logic format and a three-valued logic format according to a signal TE and a data register 3 is set by a signal DRS. Information read out from a memory array is amplified and output signals MO0...m-1, -MO0...m-1 are inputted to a binary/ three-valued logic circuit 1 while at the same time they are stored in the register 3. When the data is read out from the register 3, the register 3 is enabled by a signal DR being inputted to a counter circuit 2 and an output switching circuit 4. The circuit 2 outputs signals DR1... according to a signal C1 and the data stored in the register 3 is outputted sequentially. The switching circuit 4 delivers the output information from the logic circuit and the output information from the register 3 of 1...m bits while combining. A decision is made at which address a failure has occurred through comparsion of the information.

4. 发明专利

JPH0785697A TEST METHOD FOR SEMICONDUCTOR MEMORY AND ITS TEST SYSTEM 失效
公开(公告)号：JPH0785697A
公开(公告)日：1995-03-31
申请号：JP23181993
申请日：1993-09-17
申请人： HITACHI LTD
发明人： SAKAI YUJI , OSHIMA KAZUYOSHI , SAWADA JIRO
IPC分类号： G01R31/26 , G01R31/28 , G11C29/00 , G11C29/56
摘要： PURPOSE:To easily recognize a defect occurring condition and to shorten a time for analyzing a defect by sampling a defective bit relating to a specific defective mode. CONSTITUTION:Only a defective bit relating to a specific defective mode specified by a defect setting means 4 is sampled out of defective bits of a LS11 detected by a tester 10 with a measuring condition set by a condition setting means 2 in a defective address analyzing means 3, sent to a display means 5 and a distribution condition of defective bits is displayed, and the occurring condition of a defective mode is recognized. And when the specific defective mode is discriminated and measuring range and measuring condition required for analyzing is informed to the condition setting means 2, a controller 11 sends a signal required for a test from a power supply section 17 and a pattern generator 12 to the LS 11, read-out data is compared with write-in data in a comparator means 14, and normal/defective condition is discriminated. Thus, analyzing a cause of it occurrence of a defect can be performed quickly and easily by sampling a specific defective mode out of mixed defective modes and clarifying a defective object to be analyzed.

5. 发明专利

JPH0550080B2 失效
公开(公告)号：JPH0550080B2
公开(公告)日：1993-07-28
申请号：JP22060983
申请日：1983-11-25
申请人： HITACHI LTD
发明人： SAWADA JIRO
IPC分类号： G11C29/00 , G01R31/28 , G11C29/04 , G11C29/44

6. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

7. 发明专利

JPS63126246A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63126246A
公开(公告)日：1988-05-30
申请号：JP27183686
申请日：1986-11-17
申请人： HITACHI LTD
发明人： SAWADA JIRO
IPC分类号： H01L21/82 , H01L21/268 , H01L21/3205 , H01L27/10
摘要： PURPOSE:To calculate positions of a positioning target and a fuse piece correctly, by forming the upper layer of the target of a metal having a high reflectivity with respect to laser light while forming the lower layer of the same material as the fuse. CONSTITUTION:In order to position a fuse piece 7 for cutting it with laser light, a wafer 3 is irradiated with laser light and the laser light is scanned in the X- and Y-directions so that variance in reflectivity thereof is detected. The upper layer 1b of a target 1 is composed of a metal having a high reflectivity with respect to the laser light. Therefore, the position of the target 1 can be detected easily. The position of a fuse piece 7 connected to a defective circuit is calculated from a distance between a fuse pattern formed in a part of a gate electrode forming mask and the target pattern. The predetermined fuse piece is cut by applying laser light and the circuits are switched over.

8. 发明专利

JPS62184700A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62184700A
公开(公告)日：1987-08-13
申请号：JP2589886
申请日：1986-02-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAWADA JIRO , KATO SHIGENOBU
IPC分类号： G06F12/16 , G11C11/34 , G11C11/401 , G11C11/408 , G11C29/00 , G11C29/04
摘要： PURPOSE:To attain the high speed operation by arranging an address buffer and a redundancy circuit adjacently so as to decrease the length of an output wire viewed from the address buffer side. CONSTITUTION:Memory arrays M1L-M2R are provided respectively with the X system spare memory arrays MX1L-MX2R and the Y system spare memory arrays MY1L-MY2R. Redundancy circuits R-AC, C-AC consist of a defective bit address storage circuit and an address comparison circuit comparing a defective address signal and an address signal fed from address buffers R-ADB and C-ADB and detecting the input of the defective address and switches a spare memory array from the array of the defective bit. The redundancy circuit R-AC is arranged between the row address buffer R-ADB and its output drive circuit R-DRV and the redundancy circuit C-AC is arranged between a column address buffer C-ADB and its output drive circuit C-DRV.

9. 发明专利

JPH04350961A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04350961A
公开(公告)日：1992-12-04
申请号：JP12430791
申请日：1991-05-29
申请人： HITACHI LTD
发明人： SAWADA JIRO
IPC分类号： H01L23/538 , H01L23/522
摘要： PURPOSE:To obtain a small size semiconductor integrated circuit device by reducing a total size of a semiconductor integrated circuit device having a multichip module. CONSTITUTION:A memory module 1 has been constituted by coupling a plurality of semiconductor chips 4a to 4c with a lead wiring group 2 formed by a plurality of lead wiring 2a through insulating films 5a to 5c and electrically connecting pads 6 of semiconductor chips 4a to 4c with lead wirings 2a. Moreover, the lead wirings 2a, 2a are stacked by providing an insulating film between lead wirings 2a, 2a crossing at the lead wiring group 2.

10. 发明专利

JPH0438143B2 失效
公开(公告)号：JPH0438143B2
公开(公告)日：1992-06-23
申请号：JP18677083
申请日：1983-10-07
申请人： HITACHI LTD
发明人： SAWADA JIRO , YANAGISAWA KAZUMASA
IPC分类号： G11C11/408 , G05F3/20 , H01L21/822 , H01L27/04

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