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1. 发明专利

SG157994G Semiconductor memory 未知
公开(公告)号：SG157994G
公开(公告)日：1995-03-17
申请号：SG157994
申请日：1994-10-27
申请人： HITACHI LTD
发明人： YANAGISAWA KAZUMASA
IPC分类号： G11C11/401 , G11C11/403 , G11C11/406 , G11C11/24
摘要： Disclosed is a dynamic RAM wherein each time a refresh address counter (CT1, CT2) performs a plurality of steps of increment operations, an address switching circuit (CT3, DCR) is switched to specified refresh addresses held in an address storage circuit (RO ... R3), by utilizing the most significant bit of a divided-by-(2 + 1) counter circuit (CT1) whereby memory cells of inferior data retention times are refreshed.

5. 发明专利

FR2553558B1 未知
公开(公告)号：FR2553558B1
公开(公告)日：1991-10-04
申请号：FR8414337
申请日：1984-09-19
申请人： HITACHI LTD
发明人： YANAGISAWA KAZUMASA
IPC分类号： G11C11/401 , G11C11/4099 , G11C11/34
摘要： When half-size dummy cells are used in a dynamic memory, it is difficult to increase the relative accuracy of the capacitors in the half-size dummy cells and the capacitors in memory cells. According to the present invention, a pair of full-size dummy cells is provided connected to a pair of bit lines. High-level and low-level signals amplified by the sense amplifier are written into the full-size dummy cells, the capacitors of the pair of full-size dummy cells are then short-circuited by a short-circuiting circuit, and the electric charges in the capacitors provide a reference level. This method does not need a generator circuit providing a voltage of 1/2 VCC (Vcc: power-source voltage) which would necessitate a large quantity of power to drive it.

6. 发明专利

HK48190A DYNAMIC MEMORY 未知
公开(公告)号：HK48190A
公开(公告)日：1990-06-29
申请号：HK48190
申请日：1990-06-21
申请人： HITACHI LTD
发明人： YANAGISAWA KAZUMASA
IPC分类号： G11C11/401 , G11C11/4099 , G11C5/02
摘要： When half-size dummy cells are used in a dynamic memory, it is difficult to increase the relative accuracy of the capacitors in the half-size dummy cells and the capacitors in memory cells. According to the present invention, a pair of full-size dummy cells is provided connected to a pair of bit lines. High-level and low-level signals amplified by the sense amplifier are written into the full-size dummy cells, the capacitors of the pair of full-size dummy cells are then short-circuited by a short-circuiting circuit, and the electric charges in the capacitors provide a reference level. This method does not need a generator circuit providing a voltage of 1/2 VCC (Vcc: power-source voltage) which would necessitate a large quantity of power to drive it.

8. 发明专利

SG34380A1 Semiconductor memory device and memory module using the same 未知
公开(公告)号：SG34380A1
公开(公告)日：1996-12-06
申请号：SG1996000488
申请日：1996-01-26
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YANAGISAWA KAZUMASA , INOUE KIYOSHI , AOKI MASAKAZU , HORIGUCHI MASASHI , TSUKUI SEIICHIRO , SUZUKI SHIGERU , SASAKI TOSHIO , SUGANO TOSHIO
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G11C7/00
摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.

10. 发明专利

SG157794G Semiconductor integrated circuit device 未知
公开(公告)号：SG157794G
公开(公告)日：1995-03-17
申请号：SG157794
申请日：1994-10-27
申请人： HITACHI LTD
发明人： SATO KATSUYUKI , YANAGISAWA KAZUMASA
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C5/00 , G11C11/24
摘要： In an MOS integrated circuit device, the level of the back-bias voltage (-Vbb) which is generated by a built-in back-bias generation circuit (Vbb-G) and is supplied to a semiconductor substrate is changed by undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant but becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, the back-bias voltage generation circuit (Vbb-G) has an output capacity of a plurality of levels. The output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit (Vbb-G) can further be reduced by providing a level detection circuit (VLD) for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit (VLD)

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