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1. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

2. 发明专利

JPH0562465A BONDING OPTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0562465A
公开(公告)日：1993-03-12
申请号：JP24685191
申请日：1991-08-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： BABA TADASHI , KUMADA ATSUSHI , KATO SHIGENOBU
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To block the through currents of a bonding option circuit. CONSTITUTION:A function selecting bonding pad 18 is formed in the neighborhoods of a Vcc read and a Vss read. The pad 18 is connected with the Vcc read or the Vss read, so that the indeterminate state of the logical level of the input terminal of an invertor 26 can be removed, and the through currents can be blocked by unnecessitating a pull-up resistance.

3. 发明专利

JPH03116865A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03116865A
公开(公告)日：1991-05-17
申请号：JP25449789
申请日：1989-09-29
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MIYATAKE SHINICHI , KUMADA ATSUSHI , KAJITANI KAZUHIKO , YOSHIOKA HIROSHI , UDO SHINJI
IPC分类号： H01L21/822 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To lessen the occurrence of refresh failures by a method wherein the distances between a substrate potential generating circuit and memory cell sections are elongated respectively by a factor correspondent to an indirect peripheral circuit and a direct peripheral circuit or to a bonding pad and a direct peripheral circuit. CONSTITUTION:When a substrate voltage generating circuit 9 is arranged in a region between an indirect peripheral circuit 8 and bonding pads 3, the circuit 9 is arranged at the center of a part between the upper and the lower memory cell arrays 10. At the same time, the indirect peripheral circuit 8 and a direct peripheral circuit 7 are arranged on a region between the circuit 9 and the upper memory cell arrays 10, and the source and the drain diffusion layers of MISFETs absorb minor carriers induced in the circuit 9. The bonding pads 3 and the direct peripheral circuit 7 are arranged on a region between the circuit 7 and the lower memory cell arrays 10, and the source and the drain diffusion layers of the MISFETs arranged adjacent to them absorb minor carriers induced in the circuit 9. By this setup, a semiconductor memory device of this design can be improved in electrical reliability.

4. 发明专利

JPH06222948A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06222948A
公开(公告)日：1994-08-12
申请号：JP3144493
申请日：1993-01-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEO KIMIHARU , HISAMATSU HITOSHI , KIKUCHI HIDENORI , BABA TADASHI , KUMADA ATSUSHI
IPC分类号： G06F11/22 , G11C11/401 , G11C29/00 , G11C29/14 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent malfunction caused by power source fluctuation on the condition that one of two high voltage detection circuits detects a high voltage and the other circuit does not detect the high voltage in a special mode. CONSTITUTION:This device makes it a condition that one of two high voltage detecting circuits detects the high voltage and the other circuit does not detect the high voltage in the special mode. In this case, the device acids the condition that the special mode is set when an address terminal A1T is at a high level and an address terminal A2T is turned to a low level. Namely, the high level of the address terminal A1T and the low level of the address terminal A2T are inverted by an inverter circuit N6 and supplied to a NAND gate G3 and when the conditions for the low level of the output signal and the low level of an AND gate G4 are established, a test mode signal TSMB not to be opened is generated. On the other hand, the output of the NAND gate G3 is turned to the high level by the low level of the address terminal A1T and the output of a NOR gate circuit is fixed at the low level.

5. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

6. 发明专利

JPH01145851A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01145851A
公开(公告)日：1989-06-07
申请号：JP30319487
申请日：1987-12-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMAZAKI TAKASHI , OSHIMA KAZUYOSHI , KUMADA ATSUSHI , UDO SHINJI , TAKANO MITSUHIRO
IPC分类号： H01L27/10 , G11C11/409 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To shorten the separating interval between data lines and to improve an integration density, by making the extending direction of complementary data lines agree with the direction of the gate length of a shorting MISFET, and inverting the pattern of a complementary signal in the next stage with respect to the pattern of a preceding complementary signal. CONSTITUTION:In a DRAM, the extending direction of each complementary data line is made to agree with the direction of the gate length of a shorting MISFET QSH. Then, the deviating amount in mask alignment between a connecting part Cont and a gate electrode G of the shorting MISFET QSH is generated in the extending direction of each complementary data line DL. Therefore, the separating interval between the complementary data lines DLs is shortened. With respect to the pattern of the complementary signal of the complementary data line DL, the pattern of the complementary signal of the complementary data line DL at the next stage is inverted. Thus, two data lines (d2 and d3) are made to pass between two connecting parts Cont's between two pieces of the data line (d1 and d4) and two input/output selecting MISFET QYs. Therefore, the separating interval between the data lines can be shortened by the amount of the part, where the separating interval corresponding to the deviating amount in mask alignment is not present.

7. 发明专利

JPH09107081A SEMICONDUCTOR MEMORY AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09107081A
公开(公告)日：1997-04-22
申请号：JP8991096
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a highly integrated device with high speed, by forming a peripheral circuit in first and second regions and providing a plurality of bonding pads on the first region in a zigzag form along the first region for connecting a semiconductor substrate and the outside. SOLUTION: A memory array is formed in a four-sectional area made of cross-shaped areas A to E. Then, a Y-decoder(Ydec) and a Y-select driver (YS driver) are provided according to the upper and lower arrays made in a pair. An X-decoder(Xdec) is put in the area of C and a word line driver (WL driver) is put in the area of D. An address buffer and the like are put in the areas A and B, a common source switch circuit and the like are put in the area of C and D, and an address signal generating circuit for the X-decoder and Y decoder is put in the central area of E. In this way, a large-size semiconductor device can be realized.

8. 发明专利

JPH11330170A SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF, AND INSPECTION OF THE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11330170A
公开(公告)日：1999-11-30
申请号：JP13938898
申请日：1998-05-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： IWATA MASAKI , KUMADA ATSUSHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, a method for manufacturing the semiconductor device, and a method for inspecting the semiconductor device, which can shorten an inspection time of semiconductor devices in the form of a wafer. SOLUTION: Fuses 5 for identification of inspection results associated with respective semiconductor chips 2 are provided on streets 3 of a wafer 1, having plural semiconductor chips 2. In the method for inspecting the semiconductor devices, the fuse 5 for identification of an inspection result corresponding to the semiconductor chip 2 as a defective is cut off in the first inspection, and the semiconductor chip as the defective corresponding to the cut-off fuse 5 is not inspected in the second inspection.

9. 发明专利

JPH10256512A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10256512A
公开(公告)日：1998-09-25
申请号：JP10223198
申请日：1998-03-30
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize a high-capacity semiconductor device by placing first to fourth decoder circuits along connections of first regions and first to fourth memory arrays and fifth to eighth decoder circuits along connections of second regions and first to fourth memory arrays. SOLUTION: Memory arrays are disposed at four divided areas of a cross area composed of the longitudinal and transverse center zones of a chip; areas A and B are at the left and right of the transverse center zone, areas C and D are the upper and lower parts of the longitudinal center zone, and area E is at the cross section of both zones. Decoders and drivers for selecting the memory arrays are disposed at the periphery of the area A adjacent to the arrays, and bonding pads are disposed at the longitudinal center areas.

10. 发明专利

JPH02250372A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02250372A
公开(公告)日：1990-10-08
申请号：JP7061689
申请日：1989-03-24
申请人： HITACHI LTD
发明人： KUMADA ATSUSHI
IPC分类号： G11C11/401 , G11C11/407 , H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/10 , H01L27/108
摘要： PURPOSE:To improve integration by a method wherein word lines are connected to each other through connection holes arranged in a direction perpendicular to the word lines, and a plate feed line is extended along the connection holes in the vicinity. CONSTITUTION:Lower word lines 1 and upper word lines 2 are connected with each other through first connection holes 5 and second connection holes 6 arranged in a direction crossing their extending direction, while a plate feeding line 7 formed on the same wiring layer as that of connection wiring is provided in the direction of the connection hole arrangement in the vicinity of the holes. Thus the dimension in the direction of the word lines of a memory mat can be reduced by the amount corresponding to the arrangement size of the plate feeding line 7, thereby improving integration of a semiconductor integrated circuit.

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