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1. 发明专利

JPH0379798B2 失效
公开(公告)号：JPH0379798B2
公开(公告)日：1991-12-19
申请号：JP16099882
申请日：1982-09-17
申请人： HITACHI LTD
发明人： OONISHI YOSHIAKI , KAWAMOTO HIROSHI , YASUI NORIMASA
IPC分类号： G11C11/403 , G11C11/34 , G11C11/408

2. 发明专利

JPH0337869B2 失效
公开(公告)号：JPH0337869B2
公开(公告)日：1991-06-06
申请号：JP10466086
申请日：1986-05-09
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/78

3. 发明专利

JPS6452283A MEMORY CIRCUIT 失效
公开(公告)号：JPS6452283A
公开(公告)日：1989-02-28
申请号：JP16877088
申请日：1988-07-08
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： TANIMURA NOBURO , FUKUDA HIROSHI , NISHIMURA KOTARO , YASUI NORIMASA
IPC分类号： G11C11/41 , G11C11/34 , G11C11/417
摘要： PURPOSE:To attain a high speed access by connecting a digit line to a common data line through a column gate controlled by the output of a Y decoder and lowering the level of the digit line. CONSTITUTION:When information '1' is stored in a memory cell MS11, at the time of selecting a word line W1, transmitting gate MISFETQ3, Q4 are turned on. At this time, since a FETQ1 is turned off, to the serial connected loading means R11 of an enhancement type MISFET, a current does not pass but the digital line D11 goes to a high level lower by a voltage twice as high as the threshold voltage of the FET from VCC. A loading means R01 generates a comparatively large voltage deterioration to bring the digit line D01 to a low level. Thereby, the output lines C1-Cn of the Y decoder 3 go to a comparatively low level, from which the FETQ5, Q6 of a column input and output circuit 4 are turned on to transfer data at high speed.

4. 发明专利

JPS6135635B2 失效
公开(公告)号：JPS6135635B2
公开(公告)日：1986-08-14
申请号：JP15743278
申请日：1978-12-22
申请人： HITACHI LTD
发明人： UCHIBORI KYOBUMI , YAMAMOTO AKIRA , YASUI NORIMASA , MASUHARA TOSHIAKI , MINATO OSAMU
IPC分类号： G11C11/413 , G06F1/30 , G06F12/16 , G11C11/34 , G11C29/00

5. 发明专利

JPS60242583A MEMORY CIRCUIT 失效
公开(公告)号：JPS60242583A
公开(公告)日：1985-12-02
申请号：JP24961784
申请日：1984-11-28
申请人： HITACHI LTD , HITACHI TOKYO ELECTONICS KK
发明人： TANIMURA NOBUROU , FUKUDA HIROSHI , NISHIMURA KOUTAROU , YASUI NORIMASA
IPC分类号： G11C11/417 , G11C11/34 , G11C11/413
摘要： PURPOSE:To shorten the access time of the memory circuit by lowering the source voltage of a digit line through a load means and turning on a switch means which connects the digit line to a common data line with a small output. CONSTITUTION:The high level of digit lines D11-D1n and D01-D0n of a memory matrix drops below the source voltage VDD due to series resistances R11- R1n and R01-R0n connected to a power source. Even when the decoding output of an Y decoder 3 is small, FETs Q5, Q6... as switch means turn on speedily by said drop to connect a common data line CD1 and data lines D11-D1n and a common data line CD0 and data lines D01-D0n at a high speed, and a readout circuit which receives the signal of the CD0 operates with high sensitivity, thereby shortening the access time of the memory circuit.

6. 发明专利

JPS6089964A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6089964A
公开(公告)日：1985-05-20
申请号：JP13714684
申请日：1984-07-04
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/412 , H01L21/8234 , H01L21/8244 , H01L27/088 , H01L27/10 , H01L27/11
摘要： PURPOSE:To obtain a memory device which easily realizes refreshment by forming a dynamic FF type memory cell holding the write information charges using four MISFET elements and supplying charges as much as leakage to the information accumulating means through a load means consisting of a high resistance polycrystalline Si connected to the power supply voltage line. CONSTITUTION:A dynamic FF type memory element is formed by the FET elements Q1 and Q2 for driving and the FET elements Q3 and Q4 for transmission. These are connected by the diffusion resistances 2a, 2b, 2c consisting of polycrystalline Si. Here, 2a is the power supply line, 2b is the line connecting the elements Q1-Q4 and load resistances R1, R2, and 2c is the word line. The load resistances R1, R2 are respectively formed by the polycrystalline Si layers 3a and 3b. In this case, however, these layers have the higher resistances than the layers 2a, 2b. In addition to these elements, the true digit line 5a consisting of Al wiring, earth line 5b, bar digit line 5c, electrode wirings 6a, 6b and contact portions 7a and 7b are provided.

7. 发明专利

JPS6089963A INTEGRATED CIRCUIT MEMORY DEVICE 失效
公开(公告)号：JPS6089963A
公开(公告)日：1985-05-20
申请号：JP13714584
申请日：1984-07-04
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/417 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/10 , H01L27/11 , H01L29/78
摘要： PURPOSE:To obtain the titled device which operates by the dynamic memory system by forming a dynamic FF type memory cell with four MISFET's and additionally supplying the leak charges from an accumulation means to the accumulation means through a load means consisting of a high resistance polycrystalline silicone connected to the power supply line. CONSTITUTION:An IC memory device is formed by providing the MISFET elements Q1 and Q2 for driving, MISFET elements Q3 and Q4 for transmission and load resistances R1 and R2 between the power supply VDD line and word line. Namely, the source of element Q1 is connected to the power supply line VDD throgh the resistor R1, while the drain of element Q2 to the line VDD through the resistor R2 and the drain of element Q1 and source of element Q2 are mutually connected and then arounded. The gate of element Q1 is connected to the reistor R2, while the gate of element Q2 to the reistor R1, and the source and drain of the elements Q3 and Q4 respectively connected to the word line at the gates are respectively connected to the gate of element Q2 and the gate of element Q1.

8. 发明专利

JPS6089887A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6089887A
公开(公告)日：1985-05-20
申请号：JP13714784
申请日：1984-07-04
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/413 , G11C11/34 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To attain ease of high circuit integration and refresh operation by forming a selection signal having the relation of phase inverting. CONSTITUTION:A memory cell 68 connected to each of plural word lines, a row decoder 66 forming a selection signal commanding a prescribed number of word lines from plural word lines and a column decoder 70 applying selectively a different selection signal to a prescribed number of word lines base on the different two selection signals are provided. In this case, the two selection signals are formed in the timing phase-inverted mutually.

9. 发明专利

JPS6016469A MANUFACTURE OF MIS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6016469A
公开(公告)日：1985-01-28
申请号：JP7283584
申请日：1984-04-13
申请人： HITACHI LTD
发明人： SHIRASU TATSUMI , YASUI NORIMASA , FUKUDA MINORU
IPC分类号： H01L29/78
摘要： PURPOSE:To obtain the titled device of high withstand voltage with the reduction of element dimensions, areas, dispersion of characteristics by a method wherein a drain layer of double diffusion type is formed by self-alignment. CONSTITUTION:A field oxide film 2, gate oxide film 3, and poly Si gate electrode 4 are formed on an N type Si substrate 1, and then B ions 6 are implanted at a low concentration with a photo resist 5 as a mask. A P-layer 6a is formed by heat treatment, and a P layer 7 and a P source layer 7a shallower then the P-layer 6a are formed by heat treatment after OB ion implantation excluding to the SiO2 film 3 with the electrode 4 as a mask. At this time, the poly Si 4 is sufficiently reduced in resistance. Thereafter, Al source and drain electrodes S and D are formed by a cover of a PSG8 as normal. In this construction, high withstand voltage can be obtained because of the relaxation of the field concentration of the surface of a drain junction, resulting in the formation of drains 6a and 7 by self-alignment; therefore element dimensions can be processed with good reproducibility without dispersion. Accordingly, it becomes possible to make characteristics uniform and to reduce the element area.

10. 发明专利

JPS59112643A Complementary mis semiconductor integrated circuit device 失效
标题翻译：补偿型半导体集成电路器件
公开(公告)号：JPS59112643A
公开(公告)日：1984-06-29
申请号：JP18498683
申请日：1983-10-05
申请人： Hitachi Ltd
发明人： NISHIMURA KOUTAROU , YASUI NORIMASA , MEGURO SATOSHI
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/10 , H01L29/78
CPC分类号： H01L21/8238
摘要： PURPOSE:To provide a high resistance element in a CM1SIC without adding any new step by merely altering part of a mask pattern. CONSTITUTION:A p type well is formed in an n type layer on an n type Si substrate, and an Si3N4 film 7 on an oxidized film 6 is selectively removed by a resist mask 8. With CVD oxidized films 9, 10 as masks B and P ions are sequentially implanted, the film 7 is selectively oxidized at 11 to form a p type layer 11 and an n type layer 13, and the films 7, 6 are removed. Then, a polysilicon layer 16 is selectively formed on a gate oxidized film 15 and conducted. Subsequently. CVD oxidized film masks 17, 18 are sequentially covered, and B and P ions are implanted to form an n type layer 18 and a p type layer 20. At this time the part 21 of the polysilicon layer 16 is not ion implanted, a high resistance layer is formed, and both terminals are connected to the n type layer. According to this configuration, the diffusing masks are positively used to form the polysilicon region in which impurities of both types are not doped and to utilize it for a high resistance element.
摘要翻译：目的：在CM1SIC中提供高电阻元件，而不需要通过改变掩模图案的一部分来添加任何新的步骤。构成：在n型Si衬底上的n +型层中形成p型阱，通过抗蚀剂掩模8选择性地除去氧化膜6上的Si 3 N 4膜7。依次注入作为掩模B和P离子的CVD氧化膜9,10，在11处选择性地氧化膜7以形成p型层11和n型层13，并除去膜7,6。然后，在栅极氧化膜15上选择性地形成多晶硅层16并进行导电。后来。顺序地覆盖CVD氧化膜掩模17,18，并注入B和P离子以形成n +型层18和ap +型层20.此时多晶硅层16的部分21不是离子注入，形成高电阻层，两端连接到n +型层。根据该结构，扩散掩模被积极地用于形成其中不掺杂两种杂质的多晶硅区域，并将其用于高电阻元件。

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