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1. 发明专利

JPS60243716A VOLTAGE REGULATOR 失效
公开(公告)号：JPS60243716A
公开(公告)日：1985-12-03
申请号：JP22217184
申请日：1984-10-24
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI , NISHIMURA KOUTAROU , NARITA KAZUTAKA
IPC分类号： H01L27/04 , G05F3/24 , H01L21/822
摘要： PURPOSE:To obtain a reference voltage generator reduced at its temperature dependency and production deviation by using the Fermi level difference between two IGFETs having different conductive types of silicone gate electrodes as a reference voltage source. CONSTITUTION:Insulation gate type field effect transistors (IGFETs) T1, T2 are connected in series like a MOS diode form as shown in the figure to constitute a reference voltage generating circuit. The Trs T1, T2 are formed by an N -gate MOS and a P -gate MOS and constituted so as to have mutual conductance almost equal to the different threshold voltages Vth1, Vth2. Consequently, the difference of respective drain voltages V1, V2 becomes the difference of said threshold voltages and the difference shows the difference of the Fermi levels of the N type and P type semiconductors as a reference voltage.

2. 发明专利

JPS60201597A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS60201597A
公开(公告)日：1985-10-12
申请号：JP5428784
申请日：1984-03-23
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： NAKAMURA HIDEAKI , KUBODERA MASAAKI , NISHIMURA KOUTAROU
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C29/24
摘要： PURPOSE:To improve the remedy rate of defective elements and also to improve the read speed by providing a discharge MOSFET to the remotest end parted remotest from a driver of a word line and turning on it just before of the selection of the word line so as to eliminate the adverse effect due to a memory cell connected to a defective word line. CONSTITUTION:Drains of discharge MOSFETQ01-Q0n, Q11-Q1n and Qs1 and Qs2 are connected respectively to the start and end of the word line Ws in a sparememory row 1s and word lines W1, W2...Wn in a memory array 1, that is, a word line end close to an X decoder 3a and a word line at remote side. Sources of discharge MOSFETQ01-Q0n, Q11-Q1n and Qs1, Qa2 are connected to a ground point of the circuit, a detection signal phip outputted from an address detection circuit 8 is impressed to the gate of the MOSFETs and they are turned on temporarily.

3. 发明专利

JPS6089965A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6089965A
公开(公告)日：1985-05-20
申请号：JP13715084
申请日：1984-07-04
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/10 , H01L27/11
摘要： PURPOSE:To obtain a device of high integrating density by forming a dynamic FF type memory device to which a plurality of signals are supplied with a first and a second MISFETs which are switched by the selection signal and a third and a fourth MISFETs which are switched by the other selection signal. CONSTITUTION:The MISFET elements Q1 and Q2 for driving and MISFET elements for transmission Q3 and Q4 are formed on a semiconductor substrate, and the diffusion layers 2a, 2b, 2c consisting of polycrystalline Si are also provided for connecting these elements. Here, the layer 2a is used for power supply line, 2b for connecting the elements Q1 and Q2, Q3 and Q4, and moreover the load resistors R1 and R2. The layer 2c is used as the word line, and the resistors R1 and R2 are respectively formed by the polycrystalline Si layers 3a and 3b. In addition to such elements, the Al electrode wirings 5a-5c for true digit line, earth line are bar digit line are provided and moreover the contact portions 6a, 6b and 7a, 7b are respectively formed.

4. 发明专利

JPS59210659A Manufacture of metal oxide semiconductor device 失效
标题翻译：金属氧化物半导体器件的制造
公开(公告)号：JPS59210659A
公开(公告)日：1984-11-29
申请号：JP18498783
申请日：1983-10-05
申请人： Hitachi Ltd
发明人： NISHIMURA KOUTAROU , YASUI NORIMASA , MEGURO SATOSHI
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/8238
摘要： PURPOSE:To obtain a C-MOS.IC having excellent electric characteristics by forming a second conduction type first region and a first conduction type second region in impurity concentration higher than a first conduction type semiconductor substrate to the surface layer of the substrate through ion implantation and each forming MISFETs to these two regions. CONSTITUTION:n Type ions are implanted to the surface layer section of an n type Si substrate 1 to form an n layer 4, the whole surface is coated with an SiO2 film 2, and a window for shaping a well is bored to the film 2 while using a photo-resist film 3 as a mask. p Type impurity ions are implanted into the layer 4 in the window to form a p type well region 5, the film 2 is removed, and the whole surface is coated with a thin SiO2 film 6 again. The central sections of the surfaces of the region 5 and the layer 4 adjacent to the region 5 are coated with laminates of Si3N4 films 7 and resist films 8, and p type and n type impurity ions are implanted alternately to shape a p type region 12 and an n type region 13 positioned under a selective oxide film 11 to a boundary section between the region 5 and the layer 4. Accordingly, the substrate is prepared, and FETs are each formed demarcated by the boundary section.
摘要翻译：目的：通过离子注入形成第二导电型第一区和杂质浓度高于第一导电型半导体衬底的第一导电型第二区，获得具有优异电特性的C-MOS.IC 并且每个形成MISFET到这两个区域。构成：将n型离子注入到n型Si衬底1的表层部分以形成n +层4，整个表面涂覆有SiO 2膜2和用于成形在使用光致抗蚀剂膜3作为掩模的同时，对薄膜2无孔。 p型杂质离子注入到窗口中的层4中以形成p型阱区5，除去膜2，并再次用薄的SiO 2膜6涂覆整个表面。区域5的表面和与区域5相邻的层4的中心部分涂覆有Si 3 N 4膜7和抗蚀剂膜8的层压体，并且交替注入p型和n型杂质离子以形成ap型区域12和位于选择性氧化膜11下方的n型区域13到区域5和层4之间的边界部分。因此，准备衬底，并且每个由边界部分划定的FET。

5. 发明专利

JPS58165342A SEMICONDUCTOR IC AND PROGRAMING METHOD THEREOF 失效
公开(公告)号：JPS58165342A
公开(公告)日：1983-09-30
申请号：JP4716182
申请日：1982-03-26
申请人： HITACHI LTD
发明人： MIYAUCHI TAKEOKI , HONGOU MIKIO , YAMAGUCHI HIROSHI , MIZUKOSHI KATSUROU , KAWANABE TAKAO , MINATO OSAMU , NISHIMURA KOUTAROU
IPC分类号： H01L21/82 , H01L23/525
摘要： PURPOSE:To perform a laser diffusion program having no thermal influence upon the same by a method wherein a programing circuit for power supply and two power supply pads are provided in addition to a programing circuit to perform the final diffusion of P utilizing the Joule heat of power supply. CONSTITUTION:Circuit programing elements 2a-2z and wirings are provided on an insulative film while another wirings common to elements 2a-2z and pads 14, 15 are further provided to connect to the other ends of the wiring of said elements 2a-2z and the power supply programing elements 10a-10z, common wirings and pads are provided. When a programing high resistant poly Si wiring is irradiated by laser, the wiring is preliminarily made low resistant by a laser power much lower than the damage threshold value then the poly Si wiring is supplied with minute current to accelerate diffusion by the self heating of the high resistant section attaining to satisfactorily low resistant value.

6. 发明专利

JPS5414690A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPS5414690A
公开(公告)日：1979-02-03
申请号：JP7983877
申请日：1977-07-06
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/412 , H01L21/822 , H01L21/8244 , H01L27/04 , H01L27/105 , H01L27/11 , H01L29/78
摘要： PURPOSE:To simplify the refreshment, by composing a dynamic FF-type memory cell in which write information is stored and held in four MISFET's and by supplying the charge leakage from it to the cell via the load method of high-resistance crystal Si connected to a power voltage line.

7. 发明专利

JPS53105990A MANUFACTURE OF MOS SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS53105990A
公开(公告)日：1978-09-14
申请号：JP2022177
申请日：1977-02-28
申请人： HITACHI LTD
发明人： NISHIMURA KOUTAROU , YASUI NORIMASA , MEGURO RIYOU
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L23/52 , H01L29/78
摘要： PURPOSE:To obtain a high-resistance element of C-MOS without increasing the manufacturing processes, by altering part of the diffusion mask pattern to form a region where no P-type nor N-type impurity is not doped.

8. 发明专利

JPS6093700A LINE SWITCHING CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE USING THE CIRCUIT 失效
公开(公告)号：JPS6093700A
公开(公告)日：1985-05-25
申请号：JP19902283
申请日：1983-10-26
申请人： HITACHI LTD
发明人： SASAKI YUKIO , NISHIMURA KOUTAROU , MINATO OSAMU
IPC分类号： G11C8/08 , G11C29/00 , G11C29/04
摘要： PURPOSE:To prevent malfunction due to floating of a line and to improve the yield of a memory chip by forming a pair of transfer gates to be opened or closed complementally by a proper switching signal on the way of a transmission line to a regular memory coloumn (row) and spare redundant memory column (row). CONSTITUTION:When the switching state of a line switching circuit 17 is set up by a signal from a setting circuit 21 and the state of the circuit 17 is changed by processing a program element in a state setting circuit corresponding to a memory column including a defective bit and a selecting signal phiy is outputted from a Y decoder circuit 16, the signal is supplied to a redundant column switch 22 formed in a spare redundant memory column 12 and turns on the switch 22. Instead of the regular memory column including the defective bit, complemental data line of the redundant memory column 12 is connected to common data lines CD, CD' to read out and write data from/in the redundant memory column 12.

9. 发明专利

JPS6089889A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS6089889A
公开(公告)日：1985-05-20
申请号：JP13714984
申请日：1984-07-04
申请人： HITACHI LTD
发明人： YASUI NORIMASA , SHIMIZU SHINJI , NISHIMURA KOUTAROU
IPC分类号： G11C11/417 , G11C11/34 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To attain highly integrated circuit and high speed operation by selecting alternatively a line among plural common data lines and connecting it to a sense amplifier. CONSTITUTION:Information of different memory cell is transmitted to a data line respectively to plural common data lines and a line is selected alternatively among the plural common data lines and connected to an input of the sense amplifier. The selection circuit is provided with an MISFET placed between other common data lines connected to the input of the sense amplifier and the common data lines selected alternatively and conducted alternatively.

10. 发明专利

JPS59139727A Cmos integrated circuit device 失效
标题翻译： CMOS集成电路设备
公开(公告)号：JPS59139727A
公开(公告)日：1984-08-10
申请号：JP1272483
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： YASUI NORIMASA , OGIUE KATSUMI , NISHIMURA KOUTAROU , ODAKA MASANORI , MIYAOKA SHIYUUICHI , TAKAHASHI OSAMU , YAMAMOTO AKIRA , SASAKI KATSUROU , YOU KANJI
IPC分类号： G11C11/407 , G11C11/409 , H03K19/0185
CPC分类号： H03K19/018514
摘要： PURPOSE:To give direct access to a CMOS static RAM through an ECL circuit and to facilitate production of a CMOS IC device by using an input level converting circuit which receives a signal of a level of emitter coupled logic ECL and converts it into a CMOS signal. CONSTITUTION:An input level converting circuit is provided to a CMOS IC device to receive a signal of ECL level and converts it into a signal of MOS level. Then an external address or a control signal is supplied to the base of an nMOS FETQ10 from a terminal ECLIN. A differential nMOSFETQ9 is connected to the FETQ10, and the reference voltage Vref for level dicision is applied to the base of the FETQ9. Then a constant current source containing an nMOSFETQ13 is connected to a common source. While pMOSFETs Q11 and Q12 which work as current mirror type active loads are connected to the drains of FETs Q9 and Q10 respectively. The voltage Vref is produced by a circuit consisting of partial pressure resistances R3 and R4, MOSFETs Q1-Q8, etc. Then direct access is given to a CMOS RAM through an ECL circuit.
摘要翻译：目的：通过ECL电路直接访问CMOS静态RAM，并通过使用输入电平转换电路来促进CMOS IC器件的生产，输入电平转换电路接收发射极耦合逻辑ECL的电平信号并将其转换为CMOS信号。构成：将输入电平转换电路提供给CMOS IC器件以接收ECL电平的信号并将其转换为MOS电平的信号。然后外部地址或控制信号从端子ECLIN提供给nMOS FETQ10的基极。差分nMOSFETQ9连接到FETQ10，并且用于电平切割的参考电压Vref被施加到FETQ9的基极。然后将包含nMOSFETQ13的恒流源连接到公共源。作为电流镜式有源负载工作的pMOSFET Q11和Q12分别连接到FET Q9和Q10的漏极。电压Vref由由部分压力电阻R3和R4，MOSFET Q1-Q8等组成的电路产生。然后通过ECL电路直接接入CMOS RAM。

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