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1. 发明专利

JPH11355127A PRECHARGING CIRCUIT 失效
公开(公告)号：JPH11355127A
公开(公告)日：1999-12-24
申请号：JP16080198
申请日：1998-06-09
申请人： HITACHI LTD
发明人： YAMAUCHI TATSUMI , MURABAYASHI FUMIO , TAKAHASHI FUMIKAZU , YAMAGATA MAKOTO , KUCHIMACHI KAZUHARU
IPC分类号： H03K19/096
摘要： PROBLEM TO BE SOLVED: To reduce the delay of a data signal and to reduce power consumption by operating a first circuit and precharging a load to a high level in a precharging period, and operating a second circuit or preventing it from being operated with the combination of a clock signal and data and changing the high level of a load to a low level or holding the high level in a logic operation period. SOLUTION: In a precharging period, a clock signal CK1 is set to a high level and first N channel MOSFET 2 is turned on. Power voltage high level VDD passes through first channel MOSFET 2 by turning on first channel MOSFET 2 and load capacity 5 is precharged. Output data OUT 1 of the high level based on precharging voltage is generated to load capacity 5. In a logic operation period, the clock signal CK1 changes from the high level to a low level, first channel MOSFET 2 changes from 'on' to 'off' and the precharging of load capacity 5 is stopped.

2. 发明专利

JPH1153424A LOGIC SIMULATOR 失效
公开(公告)号：JPH1153424A
公开(公告)日：1999-02-26
申请号：JP22197097
申请日：1997-08-04
申请人： HITACHI LTD
发明人： OSONO KATSUMI , ITO MASAKI , YAMAGATA MAKOTO
IPC分类号： G06F11/25 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To reduce unnecessary inter-node communication by stopping data transmission on a transmission side as to data that are not necessary on a reception side when inter-node communication is carried out. SOLUTION: Logic data 101 is divided into nodes 105 and 107 and simulation is performed. Division information for circuit division is described previously in a division definition file 102 and a circuit dividing process part 103 distributes the logic data to nodes where it is drawn. An event deletion logic insertion part 104 extracts a memory element (flip-flop) having an enable signal, decides a memory element to which a data signal is sent form another node, propagates the enable signal, and inserts event deletion logic. In this case, when conditions indicate no need, the transmission of the data to the reception-side node is suppressed. Further, a communication control part 106 allows communication between nodes if an event occurs to a signal connecting the nodes at the time of simulation execution.

3. 发明专利

JPH0423041A DATA PROCESSOR 失效
公开(公告)号：JPH0423041A
公开(公告)日：1992-01-27
申请号：JP12753490
申请日：1990-05-17
申请人： HITACHI LTD
发明人： YAMAGATA MAKOTO , NAKANISHI JUNJI
IPC分类号： G06F9/38
摘要： PURPOSE:To control a pipeline eliminating the need for queue at a high speed with a small quantity of materials by stopping the progress of the instruction processing and its subsequent instruction processing when a queuing factor is produced at a processing stage in an instruction executing period. CONSTITUTION:When a queuing state is produced in an instruction executing period, a memory access request signal 203 is set at 1 in a 2nd cycle of the executing period. Consequently, an action queuing control signal 301 is set at 1, therefore an action control signal 401 serving as the output signal of an action control part 40 is set at 1. Thus the working of a microprogram execution control part 20 is discontinued. At the same time, an instruction control part 10 is also stopped and the state is not changed any further. Thus, the subsequent instructions included in a preparatory period are stopped when the precedent instruction during execution is stopped. Thus the processing is not carried on even if no queue is present between the pipeline elements. Thus, the data are held and a pipeline can be controlled at a high speed with no malfunction.

4. 发明专利

JPS6428758A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6428758A
公开(公告)日：1989-01-31
申请号：JP18332287
申请日：1987-07-24
申请人： HITACHI LTD
发明人： ARA MARI , SAWAMOTO HIDEO , YAMAGATA MAKOTO
IPC分类号： G06F9/46 , G06F12/10
摘要： PURPOSE:To invalidate a buffer at high speed by rewriting the identifier register of a processor to a new identifier for every invalidating processing of an address converting buffer and converting the address thereafter by the use of the address converting buffer holding the new identifier. CONSTITUTION:At the time of making access to the address converting buffer of a virtual computer, the relevant entry of the buffer 2 is made access by the use of a part of the virtual address of a logical address register 3 to compare in a comparison circuit 5 whether the virtual address part (L) read therefrom coincides with the high order address part of the register 3 or not. In the identifier VMID in the buffer 2, an identifying information value at the time of registering an entry is stored to compare in a comparison circuit 4 whether the read identifier VMID coincides with a currently travelling identification number or not. Thereafter, when the two inputs of the circuits 4, 5 coincide, an output is fed to an AND gate 6 to establish an AND condition and output a real address for a real computer to the buffer 2.

5. 发明专利

JPS6174049A Request selecting system 失效
标题翻译：请求选择系统
公开(公告)号：JPS6174049A
公开(公告)日：1986-04-16
申请号：JP19468684
申请日：1984-09-19
申请人： Hitachi Ltd
发明人： YAMAGATA MAKOTO , NINOMIYA KAZUHIKO
IPC分类号： G06F13/366 , G06F13/14
CPC分类号： G06F13/14
摘要： PURPOSE:To eliminate an empty time for selecting a channel by detecting a next channel to be processed during processing concerning one channel. CONSTITUTION:A counter 11 counts up by a clock CLK, and the output thereof is inputted to a selection circuit 10 as a selecting signal. The selection circuit 10 selects one signal designated by the selecting signal in request signals S1-Sn and the condition of the selected request signal is fed as an output signal. The selected signal is also inputted to a register 14 and set at the register 14 by an external pulse. The external pulse is delayed by a delay circuit 13 and inputted to a gate 12 together with the select signal. The output of this gate 12 is supplied to a counter 11 as a count prohibit signal.
摘要翻译：目的：通过检测在一个通道的处理期间要处理的下一个通道，消除选择通道的空闲时间。构成：计数器11由时钟CLK计数，其输出被输入到选择电路10作为选择信号。选择电路10选择由请求信号S1-Sn中的选择信号指定的一个信号，并且将所选择的请求信号的条件作为输出信号馈送。所选择的信号也被输入到寄存器14，并通过外部脉冲设置在寄存器14。外部脉冲被延迟电路13延迟并与选择信号一起输入到门12。该门12的输出作为计数禁止信号提供给计数器11。

6. 发明专利

JP2002122637A LSI DIAGNOSTIC CIRCUIT 失效
公开(公告)号：JP2002122637A
公开(公告)日：2002-04-26
申请号：JP2000314980
申请日：2000-10-16
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： SUNADA AKIRA , YAMAGATA MAKOTO , IZAKI KOJI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PROBLEM TO BE SOLVED: To guarantee exclusive control for an input signal of a selector circuit in the case that scan function-with FFs are inserted into a select path connecting a decoder logic circuit to the selector circuit. SOLUTION: Figure shows a configuration of the logic circuit applied with FF circuits. An FF circuit group having a scan function for circuit diagnosis is inserted into the select path 62 transferring logic signals (Dc0-Dc3) guaranteed in the exclusive control outputted from the decoder logic circuit 64 to the selector circuit 63. A configuration of each the FF circuit of the FF circuit group is provided with a selector circuit having one input that is a Q1 output of the FF and the other input that is a D input of the FF (an output of the decoder logic circuit 64), as shown in an uppermost circuit diagram of the FF circuit group diagram shown in Figure. The selector circuit selects and outputs one of the two inputs by control of an enable signal. The enable signal selects the Q1 output in normal operation of the logic circuit and selects the D input at the time of starting of a power source of a device or during the circuit diagnosis.

7. 发明专利

JP2000098001A TEST FACILITATING CIRCUIT 失效
公开(公告)号：JP2000098001A
公开(公告)日：2000-04-07
申请号：JP26768998
申请日：1998-09-22
申请人： HITACHI LTD
发明人： NAKAO NORINOBU , YAMAGATA MAKOTO , HATAKEYAMA KAZUMI , KOBAYASHI SEIJI
IPC分类号： H01L21/822 , G01R31/28 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit from which the overhead of a circuit area caused by the insertion of inspecting points is reduced and an analyzing method for obtaining it. SOLUTION: In a circuit to be inspected 101, observation points to signal lines 111, 121, and 131 are inserted and inserted signal lines 114, 124, and 134 are connected to a compression circuit 141, and then, the output of the circuit 141 is connected to flip flops having scanning functions through a signal line 142. Areas 112, 122, and 132 are respectively formed as the inspecting point effect areas of the observation points to the signal lines 111, 121, and 131 within the extents of signal lines traced to the input side until the signal lines reach the scanning FF group 113, 123, and 133 from the signal lines 111, 121, and 131.

8. 发明专利

JPH10105458A CACHE MEMORY SYSTEM 失效
公开(公告)号：JPH10105458A
公开(公告)日：1998-04-24
申请号：JP28152996
申请日：1996-10-02
申请人： HITACHI LTD
发明人： KURIHARA TOSHIHIKO , YAMAGATA MAKOTO
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To provide a cache which is the virtual index/real tag cache with a low association degree and where large capacitance conversion is possible and aliasing is permitted. SOLUTION: Data TLB 42 and a data cach (tag) 40 are respectively addressed by the bits 44-51, 49-56 of a virtual address and a cache TLB hit judging circuit 43 judges a hit by the output. The bits 49-51 are the object of address conversion and the bits 52-56 are an in-page real address. An alias detecting tag 50 stores a value obtained by converting a real page number in the tag 40 by a hash function, addressing is executed by the in-page real addresses (52-56) when a hit miss occurs in the judging circuit and the block transfer of data is executed, the output is compared with the value obtained by converting the real page number from the judging circuit 43 by a comparator and the entry of the cache corresponding to the position of a coincident value in the tag 50 is invalidated at the time of coincidence.

9. 发明专利

JPH0318936A INPUT/OUTPUT EXECUTING DEVICE FOR RECURSIVE VIRTUAL COMPUTER 失效
公开(公告)号：JPH0318936A
公开(公告)日：1991-01-28
申请号：JP15232889
申请日：1989-06-16
申请人： HITACHI LTD
发明人： TANAKA TOSHIHARU , UMENO HIDENORI , YAMAGATA MAKOTO , SATO HIROAKI , KUBO TAKAO
IPC分类号： G06F9/46
摘要： PURPOSE:To obtain a recursive virtual computer VM having the reduced overhead by executing directly an input/output instruction of the recursive VM with no intervention of a virtual computer control program VMCP. CONSTITUTION:An instruction processor sets the level of the program of an input/output requester at a bit in a prescribed subchannel 520-i to undergo the input/output execution when the level of the requester is decided as a recursive VM3 or VM4. Then the instruction processor sets the subchannel program address designated by an instruction at a subchannel 520 together with a subchannel number (i) at an execution subchannel number 530 and informs the start of an input/output instruction to be given to an input/output processor 300. As a result, the input/output instruction of the VM3 or the VM4 can be directly carried out with no intervention of the VMCP 510 and 610. Thus it is possible to obtain a recursive VM having the reduced overhead.

10. 发明专利

JPH02217942A AUTOMATIC PAGING SYSTEM FOR COMPUTER SYSTEM 失效
公开(公告)号：JPH02217942A
公开(公告)日：1990-08-30
申请号：JP3800589
申请日：1989-02-17
申请人： HITACHI LTD
发明人： KODA KATSUYA , YAMAGATA MAKOTO
IPC分类号： G06F12/08 , G06F12/10
摘要： PURPOSE:To reduce overhead to an operating system(OS) by executing paging processing at the level of a hardware without generating an interruption to the OS due to page exception (address conversion exception). CONSTITUTION:An automatic paging processing part 200 executes the page-in/ page-out operation of a main storage 107 and an extended storage area 108 and the updating operation of tables 106, 109. When an page exception (address conversion exception) is generated in an address conversion process, a page paged out in the area 108 is automatically read out from the area 108 without generating a page exception interruption to the OS and then paged out in a main storage area 107. Consequently, the overhead on the OS side can be reduced and the through-put of the whole system can be improved.

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