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1. 发明专利

JP2003059293A Self-test circuit 审中-公开
标题翻译：自检电路
公开(公告)号：JP2003059293A
公开(公告)日：2003-02-28
申请号：JP2001240065
申请日：2001-08-08
申请人： Hitachi Information Technology Co Ltd , Hitachi Ltd , 株式会社日立インフォメーションテクノロジー , 株式会社日立製作所
发明人： SUZUKI YASUYUKI , IZAKI KOJI , YAMAGATA MAKOTO
IPC分类号： G01R31/28 , G11C29/00 , G11C29/12 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To confirm normal operation of a register file or a RAM without requiring reduction of the number of edge pins for test and a high grade defect analyzing tool.
SOLUTION: This circuit is a self-test circuit confirming normal operation of a register file or a RAM, the circuit is constituted of an address supply section in which edge pins for general logic are used for input/output and which generates successively internal addresses, a data supply section outputting test data, a comparing circuit discriminating whether the register file or the RAM in which test data is written by comparing data read out from the register file or the RAM with expected value data generated from an internal address RAM is normal or abnormal, and a synchronization circuit synchronizing a trigger signal being not synchronous with a system clock with the system clock.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：确认寄存器文件或RAM的正常操作，而不需要减少用于测试的边缘引脚数量和高级缺陷分析工具。解决方案：该电路是确认寄存器文件或RAM的正常操作的自检电路，该电路由地址提供部分构成，其中通用逻辑的边沿引脚用于输入/输出，并且产生连续的内部地址，输出测试数据的数据提供部分，比较电路，通过将从寄存器文件或RAM读出的数据与从内部地址RAM生成的期望值数据进行比较来判别寄存器文件或其中写入了测试数据的RAM是正常的还是同步电路使与系统时钟不同步的触发信号与系统时钟同步。

2. 发明专利

JP2002122637A LSI DIAGNOSTIC CIRCUIT 失效
公开(公告)号：JP2002122637A
公开(公告)日：2002-04-26
申请号：JP2000314980
申请日：2000-10-16
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： SUNADA AKIRA , YAMAGATA MAKOTO , IZAKI KOJI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PROBLEM TO BE SOLVED: To guarantee exclusive control for an input signal of a selector circuit in the case that scan function-with FFs are inserted into a select path connecting a decoder logic circuit to the selector circuit. SOLUTION: Figure shows a configuration of the logic circuit applied with FF circuits. An FF circuit group having a scan function for circuit diagnosis is inserted into the select path 62 transferring logic signals (Dc0-Dc3) guaranteed in the exclusive control outputted from the decoder logic circuit 64 to the selector circuit 63. A configuration of each the FF circuit of the FF circuit group is provided with a selector circuit having one input that is a Q1 output of the FF and the other input that is a D input of the FF (an output of the decoder logic circuit 64), as shown in an uppermost circuit diagram of the FF circuit group diagram shown in Figure. The selector circuit selects and outputs one of the two inputs by control of an enable signal. The enable signal selects the Q1 output in normal operation of the logic circuit and selects the D input at the time of starting of a power source of a device or during the circuit diagnosis.

3. 发明专利

JPH11166961A BOUNDARY SCANNING CIRCUIT 失效
公开(公告)号：JPH11166961A
公开(公告)日：1999-06-22
申请号：JP35246697
申请日：1997-12-05
申请人： HITACHI LTD , HITACHI INFORMATION TECHNOLOGY
发明人： IZAKI KOJI , TAKAHASHI TETSUYA , YAMAGATA MAKOTO
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To reduce the overhead of a boundary scanning circuit in an LSI circuit being mounted to a JTAB circuit to a chip area. SOLUTION: One pair (1D, C1) of FF 59C of a user logic being arranged immediate after an LSI pin with two sets (1D/C1 and 2D/C2) of a pair of an input signal terminal and a clock signal input terminal is used for data input for user logic and for a system clock, the other pair (2D, C2) is used for scan data and a scan clock and a user logic FF is used also as a conventional register for updating, a boundary scan data that are transferred from a master register 59a for shifting to a slave register 59b for shifting on boundary scanning is inputted, and LSI scan in data that are inputted from an LSI pin to an FF 59C terminal 1D and are outputted from the FF output terminal are selected by a control circuit 60 according to an LSI scan mode signal 53 and are inputted to the register 59a.

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