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1. 发明专利

JPS63208230A SEMICONDUCTOR DEVICE MANUFACTURING EQUIPMENT 失效
公开(公告)号：JPS63208230A
公开(公告)日：1988-08-29
申请号：JP4025887
申请日：1987-02-25
申请人： HITACHI LTD
发明人： UNNO TASUKU , MORI YASUHIRO
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent short-circuit between lead wires and improve the yield of manufacture of a tape carrier type semiconductor device by providing a heating apparatus which heats the plated layer of lead wire surface and reduce an internal stress of such plated layer to a semiconductor device manufacturing apparatus for manufacturing a tape carrier type semiconductor device. CONSTITUTION:A film tape 3A supplied from a tape supply reel 6 is supplied to a heating apparatus 9. The heating apparatus 9 is so constituted as to heat the plated layer of lead wire mainly formed at the upper side of film tape 3A. In the case of plated layer formed of Sn, the heating apparatus 9 is formed by a heater type, hot wind type or laser type structure to heat the object up to the temperature of about 100-230 deg.C (near to the melting point of Sn). The heating apparatus 9 is formed to reduce the internal stress of plated layer. Accordingly, since generation of whisker at the surface of plated layer can be reduced, short-circuit between lead wires by whisker can he prevented. Thereby, the manufacturing yield of tape carrier type semiconductor device can be improved.

2. 发明专利

JPS6123342A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6123342A
公开(公告)日：1986-01-31
申请号：JP14238484
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： UNNO TASUKU , TOMOSAWA AKIHIRO , MEGURO HIDEO , SUZUKI NORIO , YOSHIURA AIMEI , TANIGAKI YUKIO , SHIBATA TAKASHI
IPC分类号： H01L21/768
CPC分类号： H01L21/768
摘要： PURPOSE:To prevent an exfoliation by controlling a configuration of a conductive film to be a specified area thereby minimizing a stress occurred by the difference of a coefficient of thermal expansion between the conductive film and a PSG film. CONSTITUTION:The first conductive film 3, which is composed of a high melting point metal film or a silicide film which is a compound of a high melting point metal and a silicon, is set up on the upper part of a semiconductor substrate 1 by isolating electrically. The first insulating film 4 composed of phospho silicate glass film on which a glass flow is applied to cover this first conductive film 3 is set up. Said first conductive film 3 in this semiconductor integrated circuit device is formed to be a configuration of a specified area in which the separation does not occur from the first insulating film 4. When a pattern of the conductive film 3, for instance, is a rectangle approx. to a square, the product of a side A by a side B, that is, the area is formed into a configuration in order not to be over 400mum and the stress occurred by the difference of coefficient of thermal expansion between the conductive film 3 and the insulating film 4 on it is not more than a specified value.
摘要翻译：目的：通过将导电膜的配置控制在指定区域来防止剥离，从而使导电膜和PSG膜之间的热膨胀系数的差异发生最小化。构成：由高熔点金属膜或高熔点金属和硅的化合物的硅化物膜构成的第一导电膜3通过隔离来设置在半导体衬底1的上部电气。由施加了玻璃流以覆盖该第一导电膜3的磷酸硅玻璃膜构成的第一绝缘膜4被设定。该半导体集成电路器件中的所述第一导电膜3形成为从第一绝缘膜4不发生分离的特定区域的结构。当例如导电膜3的图案为矩形大约通过侧面B的侧面A的产物，即面积形成为不超过400μm2的构造，并且应力由导电性的热膨胀系数的差异而发生膜3和其上的绝缘膜4不超过规定值。

3. 发明专利

JPS5116872A 失效
公开(公告)号：JPS5116872A
公开(公告)日：1976-02-10
申请号：JP8807074
申请日：1974-08-02
申请人： HITACHI LTD
发明人： KATO HIROSHI , ITAGAKI TATSUO , UNNO TASUKU
IPC分类号： H01L21/60

4. 发明专利

JPH07333608A LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH07333608A
公开(公告)日：1995-12-22
申请号：JP12488194
申请日：1994-06-07
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： TAKIGAWA OSAMU , KADOWAKI MASAHIKO , SATO YUKIHIRO , SASUGA MASUMI , OSONE TOMIO , OWAKI YOSHIO , WATANABE TORU , UNNO TASUKU
IPC分类号： G02B6/00 , F21V8/00 , G02F1/1335 , G02F1/13357
摘要： PURPOSE:To make it possible to reduce the thickness of a case for holding and housing a back light, etc., to realize a reduction in the thickness of a liquid crystal display device and to obtain sufficient mechanical strength. CONSTITUTION:This liquid crystal display device is constituted by holding a slope 1 by a slope 2 formed to comply with a slope 1 disposed on the rear surface of a light transmission plate 37 atop a bottom 66 of the case 65 holding this light transmission plate 37 and completely exposing a plane 4 disposed on part of the rear surface of the light transmission plate 37 from an opening 3 disposed on the bottom 66 of the case 65. The plane 4 and the rear surface 69 of the bottom 66 of the case 65 exist at the same plane and the plane 4 is fitted into part of the opening 3.

5. 发明专利

JPS61116865A Lead frame 失效
标题翻译：领导框架
公开(公告)号：JPS61116865A
公开(公告)日：1986-06-04
申请号：JP21249485
申请日：1985-09-27
申请人： Hitachi Ltd
发明人： UNNO TASUKU , KIYONO MASAMI
IPC分类号： H01L21/60 , H01L23/495
CPC分类号： H01L24/50 , H01L23/49541 , H01L2924/01082
摘要： PURPOSE:To prevent a solder from flowing out by providing a through hole at a portion connected with an electrode. CONSTITUTION:A through hole 21a is formed at the end of the lead piece 21 of a lead frame provided on a carrier tape 1. The hole 21a is formed smaller than a projecting electrode 31 on a semiconductor chip 3. The portion of the hole 21a is contacted with the electrode 31 to be heated, thereby bonding the piece 21 with the electrode 31 by a solder layer, and an excess solder layer 21a is collected in the hole 21a to eliminate the flow of the solder to the edge of the chip 3. Accordingly, a shortcircuit defect when the lead frame is bonded can be prevented.
摘要翻译：目的：通过在与电极连接的部分设置通孔来防止焊料流出。构成：在设置在载带1上的引线框架的引线片21的端部形成有通孔21a。孔21a形成为比半导体芯片3上的突出电极31小。孔21a的一部分与要加热的电极31接触，由此通过焊料层将片21与电极31接合，并且在孔21a中收集多余的焊料层21a以消除焊料流到芯片3的边缘因此，能够防止引线框架接合时的短路缺陷。

6. 发明专利

JPS5487169A DICING METHOD FOR WAFER 失效
公开(公告)号：JPS5487169A
公开(公告)日：1979-07-11
申请号：JP15447477
申请日：1977-12-23
申请人： HITACHI LTD
发明人： MORITA TADAHISA , UNNO TASUKU
IPC分类号： H01L21/301 , H01L21/302 , H01L21/78
摘要： PURPOSE:To cut the substrate of hard and feeble nature, by providing the semiconductor material, organic substrate having greater viscossity, or metal guard ring at the plane scheduled for dicing. CONSTITUTION:The guard ring 13 of Si02 is placed at the cut region 11 between element forming regions except the region 12 in contact with the blade. When cutting is made toward thicknesswise along the cut region, chipping 21 is produced at the region 11. The guard ring layer 13 absorbs the vibration at the tip of blade and becomes the cushion wall, and no chipping reaches the element region 10. With this constitution, independently of the condition of blade tip, the chipping region due to dicing is maede smaller and the integration density can be increased. Further, since no guard ring is present at the surface contacted with the blade, the life of the blade can be extended.

7. 发明专利

JPS52106676A BUMP ELECTRODE FORMING METHOD IN SEMIICONDUCTOR DEVICE 失效
公开(公告)号：JPS52106676A
公开(公告)日：1977-09-07
申请号：JP2329676
申请日：1976-03-05
申请人： HITACHI LTD
发明人： ITAGAKI TATSUO , MIYAMOTO KEIJI , UNNO TASUKU , KATOU HIROSHI
IPC分类号： H01L21/60 , H01L21/28
摘要： PURPOSE:To provide a bump electrode of high relizability by etching off all other base films with masking the bump electrode formed by applying a thin plating of Au on a Ag plating layer projected on a base metal film.

8. 发明专利

JPS63293951A SEMICONDUCTOR ELEMENT ELECTRODE STRUCTURE 失效
公开(公告)号：JPS63293951A
公开(公告)日：1988-11-30
申请号：JP12826587
申请日：1987-05-27
申请人： HITACHI LTD
发明人： TOKUNAGA KENJI , UNNO TASUKU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60
摘要： PURPOSE:To increase the number of pins, and prevent the generation of interface exfoliation, by a method wherein an internal electrode wiring is constituted as a multilayer film, for example, a Ti film is stacked on an Al film to constitute a multilayer structure, an Au diffusion layer composed of Pd is vapor- deposited on the pad of an Al/Ti multilayer film, an Al bump is formed, and many Al pads are arranged on a chip. CONSTITUTION:As an electrode structure, an Al internal electrode wiring 11 is formed on an insulating film 17 on the surface of a device 16, which wiring is formed by, e.g., sputter-deposition of Al or Al alloy. By the similar deposition, a Ti internal electrode wiring 12 is formed on the Al internal electrode wiring 11. A Ti film 13 is vapor-deposited. After a Pd layer 14 as a diffusion barrier layer of Au is vapor-deposited on the Ti film 13, an aperture is made only on a pad 19 by passing a photoresist process, and an Au bump 15 is formed by electro-plating. After that, a Pd/Ti layer except the Pd14/Ti15 layer under the Au bump 15 is eliminated to obtain an electrode structure.

9. 发明专利

JPS6329532A FILM CARRIER PACKAGE 失效
公开(公告)号：JPS6329532A
公开(公告)日：1988-02-08
申请号：JP17157086
申请日：1986-07-23
申请人： HITACHI LTD
发明人： UNNO TASUKU
IPC分类号： H01L23/28 , H01L21/60 , H01L29/06
摘要： PURPOSE:To prevent the drooping of resin and turning of the resin into a bottom surface, to perform excellent application on one surface and to improve bonding work, by providing step parts on the side surfaces of a semiconductor element, and providing a horizontal surface, which is approximately perpendicular to the side surface. CONSTITUTION:A chip 1 is attached to the lower surface of a chip potting finger lead 10 through bumps 11. The chip 1 is formed as a chip having step parts. Resin solution is potted in a device hole. After thermosetting a potting liquid 13 remains on a horizontal surface of the side surface of the chip 1. Therefore, the resin does not creep to the bottom surface and does not droop to the lower part of the bottom surface of the chip 1.

10. 发明专利

JPS59208725A Reaction apparatus 失效
标题翻译：反应装置
公开(公告)号：JPS59208725A
公开(公告)日：1984-11-27
申请号：JP8261183
申请日：1983-05-13
申请人： Hitachi Ltd
发明人： TOMOSAWA AKIHIRO , KOIKE ATSUYOSHI , UNNO TASUKU
IPC分类号： H01L21/205 , H01J37/34 , H01L21/302 , H01L21/3065
CPC分类号： H01J37/3435
摘要： PURPOSE:To uniformize reaction rate for all processing objects and uniformize reaction processings by varying area ratio of parallel falt electrodes. CONSTITUTION:A couple of parallel flat electrodes 2, 3 are provided in an etching chamber 1. A high frequency oscillation power supply 6 is connected to the upper side anode electrode 2 and the lower cathode electrode 3 is connected to the earth. The etching chamber 1 is provided with the etching gas inlet port 4 and the exhaust port 6. Moreover the cathode electrode 3 is formed so that a plurality of processing object, the wafers 7 can be placed thereon and the upper surface area can be changed by the removable rings 3b, 3c. The reaction rate of all processing objects can be uniformized and the reaction processing can also be uniformized by varying an area ratio of both electrodes 2, 3 in accordance with the reaction processing conditions.
摘要翻译：目的：使所有加工对象的反应速度均匀化，并通过不同平行的电极面积比使反应过程均匀化。构成：在蚀刻室1中设置有一对平行的平面电极2,3。高频振荡电源6连接到上侧阳极电极2，下部阴极电极3连接到地面。蚀刻室1设置有蚀刻气体入口4和排气口6.此外，阴极电极3形成为多个处理对象，晶片7可以放置在其上，并且上表面区域可以通过可拆卸环3b，3c。所有加工对象的反应速率均匀化，反应处理也可以通过根据反应处理条件改变两个电极2,3的面积比来均匀化。

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