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1. 发明授权

US6445055B2 Semiconductor integrated circuit device and manufacturing method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US6445055B2
公开(公告)日：2002-09-03
申请号：US92458801
申请日：2001-08-09
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： IWASAKII TAKAYUKI , TAKEUCHI YUSUKE , YUYAMA YOSHIAKI , TANABE SHINICHI , SAKAI KOKI , NEMOTO MINEHIRO , YUKUTAKE SEIGO , KOJIMA YASUYUKI , WATANABE ATSUO , HORIUCHI MITSUAKI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/822 , H01L21/84 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/12 , H01L29/00
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L23/5222 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor 11d in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 11a to 11d can increase the withstand voltage of a semiconductor integrated circuit.
摘要翻译：在SOI衬底的主表面上的电路区域2和由绝缘绝缘沟槽4a和4b限定的隔离区域9b通过SOI衬底中的布线电阻器或扩散电阻器11a连接。隔离区域9b和中间区域9通过SOI衬底中的布线电阻器或扩散电阻器11b连接。此外，在SOI衬底的主表面上的电路区域3和由绝缘隔离沟槽4c和4d限定的隔离区域9c通过SOI衬底中的布线电阻器或扩散电阻器11d连接。隔离区域9c和中间区域9通过SOI衬底中的布线电阻器或扩散电阻器11c连接。结果，通过布线电阻器或扩散电阻器11a至11d在电路区域2和3之间施加的电压的分布可以增加半导体集成电路的耐受电压。

2. 发明公开

EP1120915A4 OVER-SAMPLING A/D, D/A CONVERTER 审中-公开
标题翻译： ÜBERABTASTENDERA / O，D / A WANDLER
公开(公告)号：EP1120915A4
公开(公告)日：2003-10-08
申请号：EP99924006
申请日：1999-06-11
申请人： HITACHI LTD
发明人： KANEKAWA NOBUYASU , KOJIMA YASUYUKI , YUKUTAKE SEIGOU , NEMOTO MINEHIRO , TAKAMI KAZUHISA , IWASAKI TAKAYUKI , TAKEUCHI YUSUKE , FURUKAWA KATSUHIRO
IPC分类号： H03M1/00 , H03M3/00 , H03M3/02
CPC分类号： H03M3/392 , H03M3/498
摘要： Hardware for an over-sampling A/D, D/A converter capable of operating under either software handling a first method having a fixed over-sampling ratio or software handling a second method having a variable over-sampling ratio, wherein a value N3 written in a pseudo division ratio register (11) via a user interface and a value N4 written in a pseudo over-sampling ratio register (21) are converted into a division ratio N1 by a conversion circuit (12) and written in a division ratio register (10).
摘要翻译：用于能够在处理具有固定过采样率的第一方法的软件或处理具有可变过采样率的第二方法的软件下运行的过采样A / D，D / A转换器的硬件，其中写入的值N3 在经由用户接口的伪分频比寄存器（11）中，并且写入伪过采样率寄存器（21）的值N4被转换电路（12）转换为分频比N1，并被写入分频比寄存器（10）。

3. 发明专利

JPH11168412A COMMUNICATION CONTROL EQUIPMENT 失效
公开(公告)号：JPH11168412A
公开(公告)日：1999-06-22
申请号：JP33518797
申请日：1997-12-05
申请人： HITACHI LTD
发明人： MORITA YOSHINOBU , TAKEUCHI YUSUKE
IPC分类号： H03G3/30 , H03H17/02 , H04B3/06
摘要： PROBLEM TO BE SOLVED: To attain improvement in transmission characteristics. SOLUTION: When this equipment is provided with a reception amplifier 12 for amplifying a signal fetched from a line, automatic gain control circuit 24 for automatically controlling the gain of this reception amplifier 12, A/D converter 13 for converting the output signal of this circuit to a digital signal, first filter 21 for fetching that output signal and correcting the route f characteristics of the line and second filter 22 for canceling this first filter 21 left from equalization, a filter coefficient control part 23 is provided for setting the coefficient of the first filter 21 based on the tap coefficient of the second filter 22 and the gain of the reception amplifier 12 so that transmission characteristics can be improved by making proper the coefficient of the second filter 22.

4. 发明专利

JPH09214568A DRIVER AND COMMUNICATION LSI 失效
公开(公告)号：JPH09214568A
公开(公告)日：1997-08-15
申请号：JP3741196
申请日：1996-01-30
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TAKEUCHI YUSUKE , KUDO MASAKI , OKAZAKI TAKAO
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/0175 , H03K19/0948 , H03M5/16 , H04L25/49
摘要： PROBLEM TO BE SOLVED: To reduce the noise of a driver. SOLUTION: Timing control logic CONT1 and CONT2 start the supply of current to load by p-channel type MOS transistors MA3 and MB3 faster than the supply of current to a transformer 31 by p-channel type MOS transistors MA1 and MB1. Since the capacitive component of load is charged, sudden current at the time of driving load is relieved and therefore the occurrence of noise is suppressed.

5. 发明专利

JPH04227540A ARITHMETIC PROCESSOR AND DIGITAL SIGNAL PROCESSING PROCESSOR 失效
公开(公告)号：JPH04227540A
公开(公告)日：1992-08-17
申请号：JP9811691
申请日：1991-04-03
申请人： HITACHI LTD
发明人： TAKEUCHI YUSUKE
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38
摘要： PURPOSE:To provide the digital signal processing processor which can improve the efficiency of a pipelinelike arithmetic process wherein a specific arithmetic sequence is repeated. CONSTITUTION:The digital signal processing processor 1 has a first-in first-out memory 107, which is stored with coefficient data for product sum arithmetic. If the coefficient data need to be altered while the product sum arithmetic is performed repeatedly like a pipeline, the coefficient data are supplied from the first-in first-out memory 107 to a multiplier 105. The supply timing of the coefficient data is generated according to the output of a repeat counter 209 which controls the frequency of repetitive execution of the arithmetic and the supply of the coefficient data need not be indicated directly with an instruction.

6. 发明专利

JPH03273356A MICROPROCESSOR AND MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH03273356A
公开(公告)日：1991-12-04
申请号：JP7275990
申请日：1990-03-22
申请人： HITACHI LTD
发明人： TAKEUCHI YUSUKE
IPC分类号： G06F9/26 , G06F9/32 , G06F15/16
摘要： PURPOSE:To enable a high-speed processing by successively holding addresses coming after the next instruction address in a series of instructions into the second instruction address register and processing these held addresses when the head instruction of branching or changing an instruction executing operation is written into the first instruction address register. CONSTITUTION:The first and second instruction address registers 10 and 11 are provided to store the instruction addresses. This register 10 is utilized for branching or changing the instruction executing operation of a microprocessor 1, and the instruction address is transferred from an external part to the register 10. The other register 11 holds the instruction address successively incrementing the instruction address, which is outputted from the register 10, respectively only by +1 by an incrementer 14. These operations are controlled by an instruc tion address control circuit 13.

7. 发明专利

JPH02130638A DATA PROCESSOR 失效
公开(公告)号：JPH02130638A
公开(公告)日：1990-05-18
申请号：JP28488988
申请日：1988-11-11
申请人： HITACHI LTD
发明人： TAKEUCHI YUSUKE , MIKI SAKAE
IPC分类号： G06F11/22
摘要： PURPOSE:To exactly execute the analysis of defect and self-diagnosis in a short time by providing a timing generating circuit to stop the generation of a next timing signal when the generation of all the timing signals is finished. CONSTITUTION:In a microprocessor, a timing generator is provided to stop the generation of the next timing signal when a mode switching signal is inputted from an external part and the generation of all the timing signals in one machine cycle is finished. By such a means, the operation in the internal part of the microprocessor can be stopped for the unit of the machine cycle and data in a register group 3 or a RAM 4 can be held at such a time point. Then, an address is supplied from the external part or the arbitrary data are inputted from the external part to the desired register or RAM and processing can be continued by using the data. Accordingly, in a data processor such as the microprocessor to be operated according to a program, the analysis of the defect or the self-diagnosis can be exactly executed in a short time.

8. 发明专利

JP2000341181A COMMUNICATION INTERFACE DEVICE 失效
公开(公告)号：JP2000341181A
公开(公告)日：2000-12-08
申请号：JP14597499
申请日：1999-05-26
申请人： HITACHI LTD
发明人： KOJIMA YASUYUKI , KANEKAWA NOBUYASU , TAKEUCHI YUSUKE , NAMETAKE MASATAKE , NEMOTO MINEHIRO
IPC分类号： H04B3/56 , H04M19/08
摘要： PROBLEM TO BE SOLVED: To improve communication performance by making the cutoff frequency of an HPE and the cutoff frequency of an LPF lower than the cutoff frequency of a stabilizing circuit. SOLUTION: The cutoff frequency of the HPF 2 and the cutoff frequency of the LPF 5 are set much lower than the cutoff frequency of a voltage regulator 6. When the line-directional impedance is observed from a transmitting and receiving means 3 in a connection relation such as this, the parallel impedance of the cascaded impedance between a diode bridge 1, a telephone line through the HPF 2, and a station and cascaded impedance of the LPF 5 and voltage regulator 6 is seen. With characteristics like this, the impedance observed from the transmitting and receiving means 3 eventually has the impedance value of a line load passed through the HPF 2, so that the phenomenon where a transmit signal is absorbed by a power receiving circuit as a load is not generated in a frequency band in which the output of the transmitting and receiving means 3 decreases.

9. 发明专利

JP2000323650A TRIMMER CIRCUIT 失效
公开(公告)号：JP2000323650A
公开(公告)日：2000-11-24
申请号：JP13002799
申请日：1999-05-11
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TAKEUCHI YUSUKE , SEGAWA SO , KUDO MASAKI
IPC分类号： H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To obtain a technique for reducing the layout area of a trimmer circuit. SOLUTION: A first switch circuit 15-1 switches the resultant resistance of a first resistor group 14-1 according to an inputted digital signal, and a second switch circuit 15-2 switches the resultant resistance of a second resistor group 14-2 according to the inputted digital signal. Thus, the switching of the resultant resistance is operated by the first switch circuit 15-1 and the second switch circuit 15-2 so that the trimming of the resistance can be realized, and decoder for decoding the inputting digital signal can be unnecessitated. As a result, the layout area of the trimmer circuit can be reduced.

10. 发明专利

JPH1132033A LSI FOR COMMUNICATION AND COMMUNICATION CONTROLLER 失效
公开(公告)号：JPH1132033A
公开(公告)日：1999-02-02
申请号：JP18669297
申请日：1997-07-11
申请人： HITACHI LTD
发明人： MORITA YOSHINOBU , TAKEUCHI YUSUKE
IPC分类号： H04J3/06 , H04L7/08 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To reduce frame errors by providing a masking processing means for masking the frame part of input data, based on masking data set beforehand corresponding to a frame pattern in the preceding stage of a pattern detection means for detecting the frame pattern. SOLUTION: A frame detection circuit 30 performs forcible '0' discrimination on equalization data from a digital signal processing circuit based on masking information corresponding to the frame pattern and outputs the identification data. In a pattern detection circuit 32, whether or not output data from a memory 31 which stores the identification data match with a prescribed frame pattern is discriminated. Matching signals OK are asserted when the frame pattern matches, and non-matching signals NG are asserted when it does not match. In a synchronization protection circuit 35, the matching signals OK and the non-matching signals NG are respectively counter, and frame deviation signals are asserted at the point of time at which the non-matching signals NG exceed a prescribed value.

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