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1. 发明专利

AU1940597A Process for producing semiconductor integrated circuit device 未知
公开(公告)号：AU1940597A
公开(公告)日：1998-10-12
申请号：AU1940597
申请日：1997-03-14
申请人： HITACHI LTD
发明人： NISHIHARA SHINJI , IKEDA SHUJI , HASHIMOTO NAOTAKA , MOMIJI HIROSHI , ABE HIROMI , FUKADA SHINICHI , SUZUKI MASAYUKI
IPC分类号： H01L23/532 , H01L29/45 , H01L29/49 , H01L21/28 , H01L29/78

2. 发明专利

DE68928448T2 未知
公开(公告)号：DE68928448T2
公开(公告)日：1998-03-12
申请号：DE68928448
申请日：1989-01-19
申请人： HITACHI LTD
发明人： ONUKI JIN , KOUBUCHI YASUSHI , FUKADA SHINICHI , SHIOTA KATUHIKO , MIYAZAKI KUNIO , ITAGAKI TATSUO , TAKI GENJI
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52
摘要： A semiconductor device and the method of fabricating the semiconductor device include a semiconductor substrate (1) and a plurality of conductor films (2) formed on the substrate. Each of the conductor films (2) is made of aluminum alloy including at least one element selected from palladium and platinum and, more preferably, further including at least one element selected from lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chrome, hafunium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobitum, with a protective film (3) which includes oxide of the selected one of palladium and platinum being formed on the side wall of the conductor film (2).

3. 发明专利

DE68928448D1 未知
公开(公告)号：DE68928448D1
公开(公告)日：1998-01-02
申请号：DE68928448
申请日：1989-01-19
申请人： HITACHI LTD
发明人： ONUKI JIN , KOUBUCHI YASUSHI , FUKADA SHINICHI , SHIOTA KATUHIKO , MIYAZAKI KUNIO , ITAGAKI TATSUO , TAKI GENJI
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52
摘要： A semiconductor device and the method of fabricating the semiconductor device include a semiconductor substrate (1) and a plurality of conductor films (2) formed on the substrate. Each of the conductor films (2) is made of aluminum alloy including at least one element selected from palladium and platinum and, more preferably, further including at least one element selected from lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chrome, hafunium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobitum, with a protective film (3) which includes oxide of the selected one of palladium and platinum being formed on the side wall of the conductor film (2).

4. 发明专利

JP2002246390A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2002246390A
公开(公告)日：2002-08-30
申请号：JP2001042249
申请日：2001-02-19
申请人： HITACHI LTD
发明人： YAMADA YOHEI , FUKADA SHINICHI , SAEKI TOMONORI , KIKUCHI HIROSHI
IPC分类号： H01L21/3205 , H01L21/304 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device having stable characteristics. SOLUTION: After a copper film has been deposited so as to embed wiring trenches 21, 22, 23 and 24, and then the copper film on the outside of the wirings 21, 22, 23 and 24 including the upper layer of a tantalum layer 26 is polished off by a chemical mechanical polishing(CMP) method; and when a part of the tantalum film 26 is exposed, a surfactant is added to slurry, and when the outside of the wirings 21, 22, 23 and 24 is removed to completely expose the tantalum film 26, benzotriazole is added to the slurry, to thereby remove the tantalum film 26 on the outside of the wirings 21, 22, 23 and 24.

5. 发明专利

JP2001152396A SEMICONDUCTOR MANUFACTURING APPARATUS, AND SEMICONDUCTOR MANUFACTURING METHOD 失效
公开(公告)号：JP2001152396A
公开(公告)日：2001-06-05
申请号：JP33383999
申请日：1999-11-25
申请人： HITACHI LTD
发明人： SANO AKIHIRO , KOBAYASHI KINYA , FUKADA SHINICHI
IPC分类号： C25D7/12 , C25D17/10 , C25D21/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus, and a semiconductor manufacturing method in which the power is supplied from an outer peripheral part of a semiconductor wafer using an electroplating method to form a plating layer on the wafer, and the variance in film thickness caused by non-uniform contact of the semiconductor wafer with a power supply electrode can be reduced. SOLUTION: When the power is supplied onto the semiconductor wafer from the outer peripheral part of the wafer, the power is supplied to the semiconductor wafer 2 using a plurality of power supply electrodes 801-808 as shown in Fig. 1, and the current in the power supply electrodes 801-808 is kept at a preset value by constant current sources 901-908. Even when the contact of a contact surface of the power supply electrodes with the wafer is non-uniform, the current distribution along the peripheral direction of the wafer is kept uniform, and the distribution of the film thickness on the plating layer becomes uniform.

6. 发明专利

JP2000003960A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000003960A
公开(公告)日：2000-01-07
申请号：JP16549398
申请日：1998-06-12
申请人： HITACHI LTD
发明人： FUKUDA TAKUYA , FUKADA SHINICHI , KOBAYASHI NOBUYOSHI
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To enable a wiring to operate at a high speed by using an organic insulating film as an interlayer insulating film. SOLUTION: A semiconductor device is of multilayer wiring structure composed of wiring layers laminated through the intermediary of interlayer insulating films 20, 23, and 26, where the multilayer wiring structure is separated into an upper wiring sub-structure and a lower wiring sub-structure by a protective insulating film 27, and the upper wiring sub-structure comprises wiring layers mainly formed of copper and the interlayer insulating films 20, 23, and 26 formed of organic insulating film. A manufacturing method of the semiconductor device comprises a first process where the above lower wiring sub-structure is formed, a second process where annealing is carried out, a third process where the protective insulating film 27 is formed, and a fourth process where the above upper wiring sub-structure is provided by forming its wiring layers mainly of copper and interlayer insulating films of organic insulating film. Upper wiring layers required to operate at a high speed are formed of copper, and interlayer insulating films interposed between the upper wiring layers are formed of organic insulating film, whereby a wiring structure low in resistance and parasitic capacitance can be formed.

7. 发明专利

JPH11220020A MULTILAYERED WIRING STRUCTURE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11220020A
公开(公告)日：1999-08-10
申请号：JP1889798
申请日：1998-01-30
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , TAKEDA KENICHI , FUKUDA TAKUYA
IPC分类号： H05K3/46 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To alleviate and block the current concentration in a multilayered wiring structure, by connecting the regions where electric connection is performed with one or a plurality of interlayer connecting conductors, and arranging the interlayer connecting conductors in the asymmetric pattern at the side of the intersecting interior angle of the conductor-layers of a plurality of overlapped region of the second conductor layers larger than the first conductor width. SOLUTION: Lower wirings (dotted lines) 1 and upper wirings (full lines) 2 are connected by interlayer connecting wirings, so-called via wirings 3. A region 4, which is extruded in the inside, is present in the intersecting region of these upper and lower wirings. A part of the region becomes a region 5, which is recessed to the inside, between the upper and lower wirings 1 and 2. Furthermore, in the intersecting region of the upper and lower wirings, the positions of the via wirings 3, which are alinged on the diagonal line toward the outside B from the inside A, are located to the inside as a whole. Some of the plurality of via wirings 3 are located at the inner side of the intersection than the region, wherein the upper and lower wirings are externally inserted on the straight line. Since the recessed region 5 in the wiring hinders the current, the current does not flow only on the via wiring 3 located at the innermost side.

8. 发明专利

JPH10116898A WIRING FORMATION AND SEMICONDUCTOR MANUFACTURING EQUIPMENT USED THEREFOR 失效
公开(公告)号：JPH10116898A
公开(公告)日：1998-05-06
申请号：JP26693396
申请日：1996-10-08
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , KOBAYASHI NOBUYOSHI
IPC分类号： C23C14/34 , H01L21/28 , H01L21/285 , H01L21/677 , H01L21/68 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To improve coverage of interlayer connecting hole side wall by using directional sputtering method in wiring layer formation so as to perform wiring layer formation and high temperature high pressure burying by using different equipments. SOLUTION: A wiring metal layer 34 in an interlayer connecting hole is formed by a process 1, wherein a film is formed by long-range sputtering method or collimator method at temperature T1 , and a process 2, wherein the film is formed by normal direct current magnetron sputtering method at temperature T2 (T2 > T1 ). Then, the wiring metal is permitted to flow to be buried in the interlayer connecting hole 33. Thus, coverage of the interlayer connecting hole side wall is improved and degasification is prevented by using directional sputtering method for forming the wiring metal layer 34 much thicker than a high melting point metal layer.

9. 发明专利

JPH077062A METHOD FOR EVALUATING RELIABILITY OF WIRING 失效
公开(公告)号：JPH077062A
公开(公告)日：1995-01-10
申请号：JP14329993
申请日：1993-06-15
申请人： HITACHI LTD
发明人： FUKADA SHINICHI
IPC分类号： H01L21/66
摘要： PURPOSE:To evaluate the reliability of wiring against conduction irrespective of the length of the wiring by finding the fraction defective per unit length of the wiring on the basis of a specific formula at the time of performing conducting life tests which use the time until the resistance of a sample rises at a rate higher than a certain rate by conduction as the service life of the sample. CONSTITUTION:An evaluating device is constituted in such a way that an electric current is impressed on a wiring sample 2 on an Si substrate 1 from a programmable power source 8 through current impressing terminals 3 and 4 provided at both ends of the sample 2 and the voltage across terminals 5 and 6 for measuring voltage is measured, and then, the resistance of the sample 2 is calculated from the current and voltage. The reliability of the wiring is evaluated by using F(t0, m1, m2)=n(t0, m1)/L1 as the cumulative defective density per unit length of the wiring when a relation, n(t0, m1)/L1>=n(t0, m2)/L2, exists between the number of samples n(t0, m1), the conducting lives of which expire when the electric current is supplied to the samples having wiring lengths of m1 for a period of time t0, and the number of samples n(t0, m2), the conducting lives of which expire when the electric current is supplied to the samples having a total length of L2 and wiring lengths of m2 for a period of time t0. Therefore, the service life of wiring can be found irrespective of the length of the wiring.

10. 发明专利

JPH0697254A RELIABILITY EVALUATION OF WIRING 失效
公开(公告)号：JPH0697254A
公开(公告)日：1994-04-08
申请号：JP24299292
申请日：1992-09-11
申请人： HITACHI LTD
发明人： FUKADA SHINICHI , KUDO KAZUE , MINEMURA TETSUO
IPC分类号： G01R31/02 , H01L21/3205 , H01L21/66 , H01L23/52
摘要： PURPOSE:To provide a method of evaluating the service durability of a wiring independent of its length by a method wherein a specimen is subjected to a conductivity test as different currents A and B are successively applied to it, and the service life of a specimen is defined as a length of time where a current A is kept flowing through the specimen till its electric resistance increases by over a certain rate as compared with that at a test starting time. CONSTITUTION:Current applying terminals 3 and 4 and voltage measuring terminals 5 and 6 are provided to both the ends of a wiring specimen 2 formed on an Si board 1. At a conductivity life evaluating test, the specimen 2 is placed in a thermostatic chamber 7 together with the Si board 1, and a current is applied to the wiring specimen 2 through the terminals 3 and 4 from a programmable power supply 8 to start a test. At the same time, a voltage between the voltage measuring terminals 5 and 6 is measured by a direct current voltmeter 9, a time required for making the electrical resistance of the wiring specimen 2 increased by over a certain rate is obtained, and a length of time where a current A out of two different, currents A and B (A

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