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1. 发明专利

DE60028850T2 未知
公开(公告)号：DE60028850T2
公开(公告)日：2007-06-28
申请号：DE60028850
申请日：2000-01-26
申请人： HITACHI LTD , HITACHI HARAMACHI ELECTRONICS
发明人： UTSUMI TOMOYUKI , OZEKI SHOICHI , SUDA KOICHI
IPC分类号： H01L29/423 , H01L29/78 , H01L21/336 , H01L29/06 , H01L29/739
摘要： An insulated gate transistor comprising a first semiconductor region, a second semiconductor region comprising plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

2. 发明专利

DE60028850D1 未知
公开(公告)号：DE60028850D1
公开(公告)日：2006-08-03
申请号：DE60028850
申请日：2000-01-26
申请人： HITACHI LTD , HITACHI HARAMACHI ELECTRONICS
发明人： UTSUMI TOMOYUKI , OZEKI SHOICHI , SUDA KOICHI
IPC分类号： H01L29/423 , H01L29/78 , H01L21/336 , H01L29/06 , H01L29/739
摘要： An insulated gate transistor comprising a first semiconductor region, a second semiconductor region comprising plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

3. 发明专利

DE102005037788A1 未知
公开(公告)号：DE102005037788A1
公开(公告)日：2006-02-23
申请号：DE102005037788
申请日：2005-08-10
申请人： HITACHI LTD
发明人： ISHIKAWA KATSUMI , MIYAZAKI HIDEKI , SUDA KOICHI
IPC分类号： H02M1/08 , H02M7/48 , H02M7/537

4. 发明专利

JP2006054933A Inverter device 有权
标题翻译：逆变器装置
公开(公告)号：JP2006054933A
公开(公告)日：2006-02-23
申请号：JP2004232886
申请日：2004-08-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIKAWA KATSUMI , MIYAZAKI HIDEKI , SUDA KOICHI
IPC分类号： H02M1/08 , H02M7/48
CPC分类号： H03K17/168 , H02H7/0844 , H02M1/08 , H02M7/797
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable inverter device capable of detecting noises having longer cycle originating from an insulation signal transmitting element, discriminating the noises from dv/dt noises or induction noises having shorter cycle. SOLUTION: In the inverter device, a low pass filter, a band pass filter, and a switching means are arranged between an input part of the gate drive circuit of the power semiconductor switching element of a voltage drive type and an insulation signal transmitting means for transmitting the output from the control circuit. An abnormal signal judging circuit which turns on/off the switching means by the output from the band pass filter to eliminate the noises having longer cycle originating from the insulation signal transmitting element and the dv/dt noises and the induction noises both having shorter cycle, and which outputs an alarm signal, is also arranged between the input part of the gate drive circuit and the insulation signal transmitting means. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高可靠性的逆变器装置，其能够检测来自绝缘信号发送元件的较长周期的噪声，识别来自具有较短周期的dv / dt噪声或感应噪声的噪声。解决方案：在逆变器装置中，在电压驱动型的功率半导体开关元件的栅极驱动电路的输入部分和绝缘信号之间设置低通滤波器，带通滤波器和开关装置发送装置，用于发送来自控制电路的输出。一种异常信号判断电路，其通过带通滤波器的输出导通/切断开关装置，以消除源自绝缘信号发送元件的较长周期的噪声和dv / dt噪声以及具有较短周期的感应噪声，并且其输出报警信号也布置在栅极驱动电路的输入部分和绝缘信号发送装置之间。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2003339151A Mos gate drive circuit 审中-公开
标题翻译： MOS门控驱动电路
公开(公告)号：JP2003339151A
公开(公告)日：2003-11-28
申请号：JP2002147063
申请日：2002-05-22
申请人： Hitachi Haramachi Semiconductor Ltd , Hitachi Ltd , 日立原町電子工業株式会社 , 株式会社日立製作所
发明人： SUDA KOICHI , OURA HITOSHI , TANAKA TAKASHI
IPC分类号： H02M1/08 , H02M1/00
摘要： PROBLEM TO BE SOLVED: To prevent the malfunction due to dV/dt, even if the input signal pulse width of a MOS gate drive circuit is short.
SOLUTION: This MOS gate drive circuit is equipped with a pulse-generating circuit which generates an on-signal pulse and an off-signal pulse at the rise and fall, respectively, of an input signal; a high withstand voltage NMOS where these on-signal pulse and off-signal pulse are inputted; a resistor which is connected to the drain of the high withstand voltage NMOS; a level shift circuit which converts a pulse signal on the level of GND constituted of a logic circuit, based on floating potential into a signal based on floating potential, and a latch circuit which is connected to the output side of the above logic circuit. The pulse width of the off-signal pulse is set longer than the pulse width of the on signal.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了防止由于dV / dt引起的故障，即使MOS栅极驱动电路的输入信号脉冲宽度短。解决方案：该MOS栅极驱动电路配备有分别在输入信号的上升和下降时产生接通信号脉冲和截止信号脉冲的脉冲发生电路; 输入信号脉冲和截止信号脉冲的高耐压NMOS; 连接到高耐压NMOS的漏极的电阻器; 电平移位电路，其将基于浮动电位的由逻辑电路构成的GND的电平上的脉冲信号转换为基于浮置电位的信号;以及锁存电路，其连接到上述逻辑电路的输出侧。关闭信号脉冲的脉冲宽度被设定为比导通信号的脉冲宽度长。版权所有（C）2004，JPO

6. 发明专利

JP2002224756A METHOD FOR BENDING HEAT EXCHANGER 失效
公开(公告)号：JP2002224756A
公开(公告)日：2002-08-13
申请号：JP2001030377
申请日：2001-02-07
申请人： HITACHI LTD
发明人： INAGAKI NOBUO , MISEKI TAKASHI , KODAIRA SEIICHI , SUDA KOICHI , YOKOSHIMA ISAO
IPC分类号： F28F9/00 , B21D7/025 , B21D53/08
摘要： PROBLEM TO BE SOLVED: To provide a method for bending a fin and heating tube of a heat exchanger without deformation, wherein a heat exchanger for a outdoor unit of an air conditioner whose front surface area is increased to improve its performance is required to be accommodated by being bent within a space determined for miniaturization of a product. SOLUTION: A clamping accuracy of the heat exchanger is improved and a fin slide plate a is provided on a bending mold contacting the inside of the fin, even in the case of a heat exchanger whose bending and raising dimensions are short. When two types of heat exchangers 1c and 1d are bended at the same time, the fin slide plate b is disposed between the upper and lower fins, thereby enabling the bending without deformation of the fin.

7. 发明专利

JPH09172366A LEVEL SHIFT CIRCUIT AND INVERTER USING THE CIRCUIT 失效
公开(公告)号：JPH09172366A
公开(公告)日：1997-06-30
申请号：JP33150195
申请日：1995-12-20
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： OURA HITOSHI , SUDA KOICHI , KAWAMOTO KOJI , MIURA MASAHITO
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/0948 , H03K19/20
摘要： PROBLEM TO BE SOLVED: To prevent malfunction of an arm power switching element by turning off other switching elements when one switching element is turned on. SOLUTION: A dV/dt in a floating potential VM is not generated before an arm power switching element QT1 does not start turning on with an on- signal pulse from a low voltage circuit delivered to an upper arm. A resistance Ra of an off-side pulse transmission system of a level shift circuit 1 is reduced in this case by a means of the other side to reduce the resistance. Thus, a voltage drop by a resistor Rb in the on-side pulse transmission system is not caused on the occurrence of the dV/dt. Even when the occurrence of the dV/dt continues without the on-signal pulse, the signal from the off-side pulse transmission system cannot reach a flip-flop 4 by a holding function of the 'means of the other side to reduce the resistance'. Thus, even on the occurrence of the dV/dt due to self-excitation, no effect is imposed on the upper arm power switching element QT1.

8. 发明专利

JPH06196630A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06196630A
公开(公告)日：1994-07-15
申请号：JP34661292
申请日：1992-12-25
申请人： HITACHI LTD
发明人： UNTEN NOBUYASU , SUDA KOICHI , MIYAZAKI HIDEKI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain a semiconductor integrated circuit device, which can prevent the erroneous operations caused by mutual interference and noises and is suitable for use in driving devices of power converters and the like. CONSTITUTION:A power converter is constituted by forming an upper-arm driving circuit, a lower-arm driving circuit and the like in each phase in the respective semiconductor islands of a dielectric separating semiconductor substrate. A metal wiring 24 and a contact 25 are provided at a polysilicon exposed part, which is to becomes the supporting body for the dielectric separating substrate at the boundary part between the islands. The potential of the polysilicon is fixed at GND or a constant potential. The noises generated by the voltage fluctuation caused by the operation of the device are absorbed with the GND or the constant potential of the polysilicon. Thus, the erroneous operations caused by the mutual interference and the noises between the upper and lower arm-driving circuits and between the upper-arm driving circuits are prevented.

9. 发明专利

JPS644058A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS644058A
公开(公告)日：1989-01-09
申请号：JP15770487
申请日：1987-06-26
申请人： HITACHI LTD
发明人： SUDA KOICHI , TSUKUDA KIYOSHI , KARIYA TADAAKI , MATSUZAKI HITOSHI
IPC分类号： H01L21/762 , H01L21/76 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78
摘要： PURPOSE:To eliminate occurrence of latch up completely, by employing a dielectric isolation technique for insulation between a vertical type MOS and a horizontal type MOS in an output circuit part of high breakdown strength. CONSTITUTION:A dielectric isolation substrate on an output circuit part of high breakdown strength is composed mostly of a polycrystalline semiconductor substrate 13. P-type single-crystal semiconductor regions 15 to 17 are buried insularly with a dielectric film 14 in between on a main surface 11 side of this substrate. Two n-type layers and p type layers serving as sources in the n-type layers are formed in the region 15 so as to compose a vertical type p-MOS. Two n type layers serving as a source and a drain respectively are formed in the region 17 so as to compose a horizontal type n-MOS. P-type single-crystal layers 15' and 16' are formed to penetrate through dielectric films on the bottom parts in the region 15 and 16 and extended to an electrode layer 8 formed on a main surface 12 of this substrate. Such composition realizes good endurance to latch up and high integrity.

10. 发明专利

JPS6322633B2 失效
公开(公告)号：JPS6322633B2
公开(公告)日：1988-05-12
申请号：JP15218181
申请日：1981-09-28
申请人： HITACHI LTD
发明人： MATSUKUMA KUNIHIRO , SUDA KOICHI , SAKAGAMI TADASHI
IPC分类号： H01L31/0224 , H01L31/04 , H01L31/06 , H01L31/068

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