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1. 发明专利

JPS60243716A VOLTAGE REGULATOR 失效
公开(公告)号：JPS60243716A
公开(公告)日：1985-12-03
申请号：JP22217184
申请日：1984-10-24
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI , NISHIMURA KOUTAROU , NARITA KAZUTAKA
IPC分类号： H01L27/04 , G05F3/24 , H01L21/822
摘要： PURPOSE:To obtain a reference voltage generator reduced at its temperature dependency and production deviation by using the Fermi level difference between two IGFETs having different conductive types of silicone gate electrodes as a reference voltage source. CONSTITUTION:Insulation gate type field effect transistors (IGFETs) T1, T2 are connected in series like a MOS diode form as shown in the figure to constitute a reference voltage generating circuit. The Trs T1, T2 are formed by an N -gate MOS and a P -gate MOS and constituted so as to have mutual conductance almost equal to the different threshold voltages Vth1, Vth2. Consequently, the difference of respective drain voltages V1, V2 becomes the difference of said threshold voltages and the difference shows the difference of the Fermi levels of the N type and P type semiconductors as a reference voltage.

2. 发明专利

JPS60243715A ELECTRONIC DEVICE 失效
公开(公告)号：JPS60243715A
公开(公告)日：1985-12-03
申请号：JP22216384
申请日：1984-10-24
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI
IPC分类号： H03F3/45 , G05F1/56 , G05F3/24 , H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain a reference voltage generator reduced at its temperature change by using Fermi levels of two IGFETs having different conductive types of silicon gate electrodes to form a reference voltage source. CONSTITUTION:A P -gate MOSFETQ1 and an N -gate MOSFETQ2 constituting a differential pair are constituted so that their conductance values are equal. If it is defined that the current values of a constant current source for the differential circuit are I0-I''0, the intersected points 1-1'' of the current values I0-I''0 with the FETQ1 and the intersected points 2-2'' with the FETQ2 show respective gate voltages VG1, VG2 obtained when the differential circuit is balanced. Even if the current of the constant current source is changed from I0 to I'0 and I''0, the differential voltage between said gate a voltages VG1 and VG2 is kept at a constant level and the difference Vth1-Vth2 between the threshold voltages of the FETs Q1 and Q2 appears as it is. Consequently, the P -gate and N -gate FETs Q1, Q2 can be used, a reference Voltage corresponding to a band gap is obtained and the temperature characteristics can be set up to ''0''.

3. 发明专利

JPS6057660A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6057660A
公开(公告)日：1985-04-03
申请号：JP16497583
申请日：1983-09-09
申请人： HITACHI LTD
发明人： YOU KANJI
IPC分类号： H01L29/78 , H01L21/8249 , H01L27/06 , H01L27/07
摘要： PURPOSE:To contrive accomplishment of high integration by a method wherein a bipolar transistor and one FET of CMIS (complementary metal insulator semiconductor) are provided on the same Si substrate, thereby enabling to unnecessitate an insulation isolation region and to have a wiring connection region used common for a bipolar device and the FET. CONSTITUTION:The N layer 6 on a P type Si substrate 5 is surrounded by an N buried layer 7 and a P layer 9, and its surface is siolated by an oxide film 8. P-bases 12 (B1 and B2), a P connection layer 13, and N emitters 14 (E1 and E2) are provided on one island region, an N connection layer 11 is formed on the N layer (collectors C1 and C2), the source S1 and the drain D1 of a P layer 16 are provided, and bipolar transistors T1 and T2 and a P-ch MISFET Q1 is formed. At this time, an isolation layer is unnecessitated between both materials above-mentioned, and the degree of integration can be improved. When a well 17 is provided on another island and an N-ch MISFET Q2 is provided using an N layer 18 as a source S2 and a drain D2, no latch-up phenomenon is generated on the FETs Q1 and Q2, and a circuit 3 is protected by providing a poly Si resistor R between an external terminal 1 and an input buffer circuit 3. An oxide film 10, an electrode wiring T and a PSG20 are formed and the titled device is completed.

4. 发明专利

JPS6037820A INPUT AND OUTPUT CIRCUIT IN LOGICAL LSI 失效
公开(公告)号：JPS6037820A
公开(公告)日：1985-02-27
申请号：JP14497583
申请日：1983-08-10
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU MASAYUKI , YOU KANJI
IPC分类号： H03K19/0185 , H03K19/173
摘要： PURPOSE:To decrease number of required components and to decrease the occupied area by sharing a part of elements for an input/output buffer circuit and a Schmitt circuit through the change of wirings. CONSTITUTION:The 1st stage inverter consists of PMOSFETs Q1, Q3 and an NMOSFETQ2. A drain terminal of the FETs Q1, Q3 and output nodes n1, n1' are separated, and in constituting the input buffer circuit, the FETQ1 and the node n1 are connected and in constituting the Schmitt circuit, the FETQ3 and the node n1' are connected at aluminum wiring. Thus, an FETQ2 is used in common for both the circuits. On the other hand, the PMOSFETs Q4, Q5 and the NMOSFETQ5 constitute an inverter 2 of the output stage. The drain terminal of the FETQ6 and a node n1'' are separated and they are connected together only in constituting the Schmitt circuit.

5. 发明专利

JPS5539607A REFERENCE VOLTAGE GENERATION DEVICE 失效
公开(公告)号：JPS5539607A
公开(公告)日：1980-03-19
申请号：JP11171978
申请日：1978-09-13
申请人： HITACHI LTD
发明人： MEGURO RIYOU , YAMASHIRO OSAMU , YOU KANJI
IPC分类号： H03F3/345 , G11C5/14 , H01L21/822 , H01L27/04 , H01L27/088 , H01L29/78 , H03F3/34 , H03F3/45 , H03K3/0233 , H03K19/003 , H03K19/0185
摘要： PURPOSE:To obtain reference voltage with few variations and no need of adjustment after manufacturing by detecting the energy gap between Si semiconductors or the voltage smaller than this gap. CONSTITUTION:P layers 5 are formed on an N-type Si substrate 1 and N layers 6 are formed in a P-island 2. P-type and N-type polycrystal Si 7, 8 and intrinsic polycrystal Si 9 are selectively formed on each gate oxdation film. Then, with an insulation coating electrodes are provided to form P-channel FETA, B, C and N-channel FETD, E, F. Differences in Fermi levels between electrodes 7, 8 and 9 are taken out as reference voltages. Since the Fermi levels are little dependent on temperature, the differences in threshold voltages are also little dependent on temperature. When counecting drains and gates of FETT1, T2 in common and then operating thus obtained device at constant current I0, the difference in threshold voltages can be taken out from the difference in drain voltages because FETT1, T2 are different in their threshold voltages and equal in mutual conductances. Difference in Fermi levels between N-type and P-type semiconductors are obtained with use of N and P gate MOS.

6. 发明专利

JPS53144376A TIME MEASURING CIRCUIT 失效
公开(公告)号：JPS53144376A
公开(公告)日：1978-12-15
申请号：JP5870177
申请日：1977-05-23
申请人： HITACHI LTD
发明人： TORII SHIYUUICHI , ARAI TAMOTSU , YOU KANJI , AKAZAWA TAKASHI , SAKAMOTO TAKASHI
IPC分类号： G04F10/10 , H03K17/22
摘要： PURPOSE:To prevent the occurrence of erroneous setting of memory initial value at the turning on of power source with a simple circuit constitution by controlling releasing of clear locking through control circuit with clock pulses which do no mutually overlap and vary in phase.

7. 发明专利

JPS5326556A ASTABLE MULT IVIBRATOR 失效
公开(公告)号：JPS5326556A
公开(公告)日：1978-03-11
申请号：JP10057476
申请日：1976-08-25
申请人： HITACHI LTD
发明人： YOU KANJI
IPC分类号： H03K3/354
摘要： PURPOSE:To obtain a stabilized oscillation frequency by forming the bias circuit in an integrated circuit.

8. 发明专利

JPS6121515A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS6121515A
公开(公告)日：1986-01-30
申请号：JP20176684
申请日：1984-09-28
申请人： Hitachi Ltd
发明人： YOU KANJI , YAMASHIRO OSAMU
IPC分类号： G05F3/24
CPC分类号： G05F3/245
摘要： PURPOSE:To attain generation of a reference voltage with less fluctuation due to temperature change by constituting an MOS diode where a drain and a gate are connected in common by an MISFET so as to attain ease of design and mass- production of an electronic circuit. CONSTITUTION:T1, T2 are MISFETs to constitute the MOS diode where the drain and gate are connected in common. Further, the T1, T2 have different threshold voltages and nearly equal mutual conductances and a difference of the threshold voltage is extracted by taking the difference of drain voltages V1, V2. Moreover, the difference of the Fermi level of N and P channel semiconductors nearly equal to the difference of the threshold voltages is extracted by using an N gate MOS and a P gate MOS. Thus, the design and mass-production of the electronic circuit is attained easily and a reference voltage where the fluctuation of voltage and temperature change is small is generated.
摘要翻译：目的：通过构成通过MISFET共同连接漏极和栅极的MOS二极管来实现由于温度变化而产生具有较小波动的参考电压，从而实现电子电路的设计和大规模生产。构成：T1，T2是构成MOS二极管的MISFET，漏极和栅极共同连接。此外，T1，T2具有不同的阈值电压和几乎相等的互导，并且通过取出漏极电压V1，V2的差来提取阈值电压的差。此外，通过使用N栅极MOS和P栅极MOS提取近似等于阈值电压的差的N和P沟道半导体的费米能级的差异。因此，容易实现电子电路的设计和批量生产，并且产生电压和温度变化波动小的参考电压小。

9. 发明专利

JPS60252924A CONSTANT CURRENT CIRCUIT 失效
公开(公告)号：JPS60252924A
公开(公告)日：1985-12-13
申请号：JP20176884
申请日：1984-09-28
申请人： HITACHI LTD
发明人： YOU KANJI , YAMASHIRO OSAMU
IPC分类号： H01L27/04 , G05F1/56 , G05F3/24 , H01L21/822
摘要： PURPOSE:To obtain a constant current circuit having high accuracy by extracting the output of a reference voltage generating circuit of an FET produced based on the Fermi level difference of a gate electrode via a differential amplifier in the form of the output current of a current mirror circuit. CONSTITUTION:A reference voltage generating circuit is provided with an FET having the difference of threshold voltage (Vth1-Vth2) based on the Fermi level difference of a gate electrode and the same mutual conductance beta. Then the voltage drop IoutR21 caused by a current I flowing to an FET22 is compared with the reference voltage Vref. Then the beat voltage at one side of the reference voltage generating circuit is controlled in order to obtain the coincidence of said comparison at all times. In this case, Iout=Vref/R is satisfied.

10. 发明专利

JPS60150113A REFERENCE VOLTAGE GENERATOR 失效
公开(公告)号：JPS60150113A
公开(公告)日：1985-08-07
申请号：JP24952684
申请日：1984-11-28
申请人： HITACHI LTD
发明人： YOU KANJI , YAMASHIRO OSAMU
IPC分类号： G05F3/24
摘要： PURPOSE:To obtain a constant voltage output circuit suited to a monolithic IC by producing the reference voltage according to the difference of threshold voltage between the 1st and 2nd insulated gate type field effect transistors. CONSTITUTION:The p type areas 4 and 5 serving as the source and the drain of an MISFET are formed on an n type semiconductor substrate 1. A gate insulated film 2 is formed on the surface of the substrate 1 between both areas 4 and 5, and a polysilicon layer is formed on the film 2. An impurity (n type) of the same conduction type as the substrate 1 is mixed into the polysilicon layer which forms a gate 6' of an MISFETQ1. While an impurity (p type) adverse to the substrate 1 is mixed into the polysilicon layer forming a gate 6 of an MISFETQ2. The threshold values of both FETs Q1 and Q2 are obtained by equations respectively, and the voltage difference between both threshold values is equal to a difference (phiMp-phiMn) of the work function. This difference can be defined as the voltage corresponding to the energy gap of the silicon.

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