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1. 发明专利

JP2006277870A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006277870A
公开(公告)日：2006-10-12
申请号：JP2005098027
申请日：2005-03-30
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , OSAKA HIDEKI , IDO TATSUMI , NAGASHIMA YASUSHI , KATAGIRI MITSUAKI , ANJO ICHIRO
IPC分类号： G11C11/401
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C11/4074 , G11C11/4096 , H01L24/50
摘要： PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of a command/address external terminal group and a data input/output terminal group to the level of a 1-chip article, in a semiconductor storage device provided with a plurality of laminated memory chips. SOLUTION: The semiconductor storage device comprises a base board 101 provided with the command/address external terminal group CA, the data input/output external terminal group DQ and a single-chip selection external terminal CS, and the plurality of memory chips 110-113 laminated on the base board 101 and capable of reading operation and writing operation independently, respectively. The terminals CA, DQ and CS are all connected to an interface chip 120. The interface chip 120 is provided with a chip selection signal generating circuit, capable of individually activating the plurality of memory chips 110-113, on the basis of address signals supplied via the terminal CA and chip selection signals supplied via the terminal CS. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了将命令/地址外部端子组和数据输入/输出端子组的寄生电容减小到1芯片制品的水平，在设置有多个层叠的半导体存储装置中内存芯片解决方案：半导体存储装置包括设置有命令/地址外部端子组CA，数据输入/输出外部端子组DQ和单片选择外部端子CS的基板101，以及多个存储器芯片 110-113分别层叠在基板101上，并且能够分别独立地读取操作和写入操作。端子CA，DQ和CS都连接到接口芯片120.接口芯片120设有芯片选择信号发生电路，其能够基于提供的地址信号单独激活多个存储器芯片110-113 经由终端CA和经由终端CS提供的芯片选择信号。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2001067870A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001067870A
公开(公告)日：2001-03-16
申请号：JP24582099
申请日：1999-08-31
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MORITA SADAYUKI , SAKATA TAKESHI , HANZAWA SATORU , SONODA TAKAHIRO , TADOKORO HARUKO , ICHIKAWA HIROSHI , NAGASHIMA YASUSHI
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/4076
摘要： PROBLEM TO BE SOLVED: To obtain an SDRAM for switching to either SDR(single data rate) operation or DDR(double data rate) operation. SOLUTION: When SDR specifications are selected according to the first state of an external terminal (OPT) in an SDRAM, data being read from a memory mat is outputted in response to a clock signal being formed by a clock reproduction circuit with a function for judging the phases of the input and output. On the other hand, when the DDR specifications are selected according to the second state of the external terminal (OPT), data being read from the memory mat are outputted in response to the clock signal being outputted from a clock signal output circuit in synchronization with an external clock.

3. 发明专利

JP2000187985A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2000187985A
公开(公告)日：2000-07-04
申请号：JP36588798
申请日：1998-12-24
申请人： HITACHI LTD
发明人： SAKAMOTO TATSUYA , NAGASHIMA YASUSHI , TAKEMURA RIICHIRO
IPC分类号： G11C11/409 , G11C7/06 , G11C7/18 , G11C11/401 , G11C11/407 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To attain the stabilization of operation and the increase of speed for an amplifier by applying the operating voltage to a sense amplifier in accordance with the change of a switch control signal, transmitting an amplified signal formed with the amplifying operation to an input/output line by a column selection signal, and turning back the switch control signal to a selected level in accordance with the selection operation of a column selection circuit. SOLUTION: When a sub-word line SWL is selected, a shared selection signal SHR corresponded to a sub-array at the non-selected is made to a non-selected level such as a grounding potential of the circuit. Consequently, the sense amplifier is separated off from a complementary bit line at the right side, and the minute voltage difference corresponded to the stored electric charge of a memory cell which is selected by complementary bit lines BLT and BLB at the left side, is generated. A sense node SAB becomes to have the large signal amount by the connection with the bit line BLB having the large parasitic capacity through a switch MOSFET Q2.

4. 发明专利

JP2000113697A SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000113697A
公开(公告)日：2000-04-21
申请号：JP28068398
申请日：1998-10-02
申请人： HITACHI LTD
发明人： BAN NAOTO , NAGASHIMA YASUSHI
IPC分类号： G11C29/04 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can inspect a pseudo- relief state equivalent to that after a relief after a fuse is blown in a probe inspection before the reilef before the fuse is blown and to provide its manufacturing method. SOLUTION: In a DRAM, a memory cell array, an address buffer, a decoder, a relief circuit and the like are installed. A row-based pseudo-ralief circuit and a column-based pseudo-relief circuit which are built in a row-based relief circuit and a column-based relief circuit are constituted of a row-based pseudo- relief register 11 and a column-based pseudo-relief register 12 which hold a pseudo-relief address signal so as to correspond to a pseudo-relief state squivalent to that after a relief before the relief. In addition, they are constituted of a row-based relief judgment circuit 13 and a column-based relief judgment circuit 14 which compare an input address signal with the pseudo-relief address signal and which output a judgment signal used to set a pseudo-relief state squivalent to that after the relief before the relief when both signals are identical. A probe inspection in the pseudo-relief state is performed before the relief, and a probe inspection after the relief can be omitted.

5. 发明专利

JPH11316621A CLOCK SYNCHRONIZING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11316621A
公开(公告)日：1999-11-16
申请号：JP34727298
申请日：1998-12-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA HIROMASA , NAGASHIMA YASUSHI , IDEI YOJI , AOKI MASAKAZU , TANAKA HITOSHI
IPC分类号： G11C11/407 , G06F1/10 , G11C11/4076 , H03K5/13 , H03L7/00
摘要： PROBLEM TO BE SOLVED: To provide a clock circuit which has high accuracy and high responsiveness by constructing a grid-like delay circuit, successively and inputting input clock signals delayed in a 1st signal transmission direction and acquiring the output signals via the output terminals of plural logical means arrayed in the 1st signal transmission direction at the final stage of a 2nd signal transmission direction. SOLUTION: An output pulse CDMout is supplied to a grid-like delay circuit SQUAD1, and the delayed signal of the circuit SQUAD1 is supplied to an edge detection circuit ED2. The circuit ED2 compares the edge of the delayed signal of each stage of the circuit SQUAD1 with the edge of a clock pulse that is delayed more by a single clock and inputted. When both edges match with each other in terms of time, the final stage of the circuit SQUAD1 is detected. Then a multiplexer MPX3 is controlled by a detection signal CNTLB that is produced by the circuit ED2, and an output pulse EDout is outputted from a grid-like delay circuit SQUAD2.

6. 发明专利

JPH11306796A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH11306796A
公开(公告)日：1999-11-05
申请号：JP10882198
申请日：1998-04-20
申请人： HITACHI LTD
发明人： ICHIKAWA HIROSHI , NAGASHIMA YASUSHI
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To reduce the required number of pads in the probe test of a synchronous DRAM or the like and to reduce its test costs. SOLUTION: In a synchronous DRAM or the like which takes an address multiplex system, in an ordinary operating mode, row addresses RAn(H), RAn(L) and column address es CAn(H), ACn(L) are input in a time-sharing manner in one cycle from, e.g. 14 address input terminals A0 to A13. In a test mode using a probe tester, the row addresses RAn(H), RAn(L) and the column addresses CAn(H), CAn(L) are further divided respectively into, e.g. high-order bits and low-order bits so as to be input in a time-sharing manner in two cycles from, e.g. seven address pads A0 to A6 corresponding to the low-order bits.

7. 发明专利

JPH09288894A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09288894A
公开(公告)日：1997-11-04
申请号：JP12239796
申请日：1996-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To make the cycle time of a ferroelectric memory adopting a plate selection system high-speed and to stabilize the reading operation of the ferroelectric memory of large capacity and to reduce power consumption of the memory. SOLUTION: Plate lines VPL0 to VPL7 are made to be effective levels before selection operations of specified word lines are started and the lines are made to be ineffective levels after the word lines are made to be non-selection states. At this time, the effective levels of the plate lines VPL0 to VPL7 are made to be the level of a binary value readout signal in bit lines, that is, the intermediate potential HVC between a power source voltage VCC and a ground potential VSS and the ineffective levels of them are made to be the power source voltage VCC or the ground potential VSS being the precharge potential of the bit lines. Moreover, the memory array of the ferroelectirc memory is divided into plural memory array blocks MAB0 to MAB7 by making complementary bit lines B00* to B0n* or B70* to B7n*, for example, of n+1 pairs a unit and respective array blocks are selectively made to be activated states by making corresponding plate lines VPL0 to VPL7 effective levels like the intermediate potential HVC.

8. 发明专利

JPH09288893A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09288893A
公开(公告)日：1997-11-04
申请号：JP12239696
申请日：1996-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , NARUI SEIJI , SUZUKI TSUYUKI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/404 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To realize ferroelectric memories such as shadow RAM and so forth capable of raising S/N in respective modes simultaneously and also setting its capacitive coupling ratios easily. SOLUTION: At the time of a recall mode, high levels are supplied to electrodes of other sides of capacitors Csa, that is, to plate lines PL0a∼PLma and low levels are supplied to electrodes of other sides of capacitors Csb, that is, to plate lines PL0b∼PLmb and at the time of a read or write mode by a volatile mode, low levels of the same potentials are supplied to these plate lines. Thus, coupling ratios at the time of a recall operation are made large by making capacitors Csb act as load capacitances and at the time of the volatile mode, capacitive coupling ratios at the time of a normal readout operation are made small by making capacitors Csb act as information storage capacitances.

9. 发明专利

JPH04335293A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04335293A
公开(公告)日：1992-11-24
申请号：JP10554391
申请日：1991-05-10
申请人： HITACHI LTD
发明人： NAGASHIMA YASUSHI , KAJIMOTO TAKESHI , AKIYAMA NOBORU
IPC分类号： G11C11/401
摘要： PURPOSE:To speed up write in operations of systems such as a serial access memory by dividing up a memory array into k pices making k address simultaneously in a selected condition and writing in input data according to the corresponding flag bits using k pieces of write amplifier. CONSTITUTION:A write in controlling circuit WCTL selectively configure buffer control signals b0 to b3, flag signals f0 to f3, internal control signals dc and wc based on internal control signals and bit address signals a0 and a1. Then, an inut buffer IB successively takes in the input data through a terminal SIO when it is a write mode and transmits the data to data buffers DB10 to 13. DB10 to 13 successively take in and hold the input data and f0 to 3 and transmit them to write amplifiers WAO to 3 through data buffers DB20 to 23. WAO to WA 3 selectively become an operating condition provided that wc and f0 to f3 are together in an 'H' condition. Thus, the write operations easily become high speed.

10. 发明专利

JPH04143994A MULTI-PORT MEMORY 失效
公开(公告)号：JPH04143994A
公开(公告)日：1992-05-18
申请号：JP26558690
申请日：1990-10-03
申请人： HITACHI LTD
发明人： NISHIMOTO KENJI , KITANO JUN , HATANO SUSUMU , OOISHI TSURATOKI , NAGASHIMA YASUSHI
IPC分类号： G11C11/41
摘要： PURPOSE:To prevent the logic value of a readout signal from changing undesirably by a write signal via coupling capacitor by employing twist structure in which the mutual positions of a pair of complementary bit lines are switched on the middle way. CONSTITUTION:The pairs of complementary bit lines DRi, DRi* and DLi, DLi* neighboring with each other are remarked, and when write data is sup plied to the pair of complementary bit lines DLi, DLi* at the opposite side and they are driven complementarily at a time when the pair of complementary bit lines DRi, DRi* are changing complementarily by receiving the readout signal from a memory cell, the levels of the pair of DRi, DRi* are increased according to the level change of the line DLi by the influence of the coupling capacitor interlocking with the above driving. At this time, the coupling capaci tor of the pair of bit lines DRi, DRi* for the line DLi are nearly equal due to the twist structure of the pair of complementary bit lines, therefore, the level change of the pair of DRi, DRi* can be equalized with each other, and the undesired logic inversion of readout data can be prevented from occurring.

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