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1. 发明专利

JPH09245486A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09245486A
公开(公告)日：1997-09-19
申请号：JP7322496
申请日：1996-03-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To achieve a lower power consumption of a shadow RAM or the like by curtailing a required current especially in a recall mode and in a refreshing mode of the shadow RAM or the like. SOLUTION: A pair of memory arrays ARY0 and ARY1 is so arranged to be alternately made active selectively and sequentially and sense amplifiers SA0 and SA1 are so arranged to be selectively made ready with the supply of a power source voltage VCC or a ground voltage VSS to common source wires CSP0 and CSN0 or CSP1 and CSN1 corresponding to the pair of memory arrays ARY0 and ARY1. Short-circuiting switches P1 and N1 are provided respectively between the common source lines CSP0 and CSP1 and CSN0 and CSN1 to be temporarily turned ON until a corresponding sense amplifier SA0 or SA1 is made ready after the operation of selecting the word lines.

2. 发明专利

JPH09288892A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09288892A
公开(公告)日：1997-11-04
申请号：JP12239596
申请日：1996-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To reduce power consumption of ferroelectric memories such as shadow RAM and so forth and also to shorten, for example, the recovery time from a stand-by time of a system including these memories by improving convenience of the shadow RAM or the like. SOLUTION: In ferroelectric memories of the shadow RAM having a nonvolatile mode and a volatile mode or the like, a recall register RREG storing addresses of word lines in which recall operations for moving from the nonvolatile mode to the volatile mode are already excited or storing execution states of the recall operations every word line and a mode changeover circuit MODC selecting and determining operation modes of the shadow RAM or the like together with addresses given from the outside at the time of accesses and the retention information of the recall register RREG are provided Then, the recall operations are selectively executed only as to word lines which became access objects and also reflesh operations are executed only as to word lines to which the recall operations are executed or the recall operations concerning to all word lines are executed in unison in reflesh operations to be performed at first time after the supplying of power source.

3. 发明专利

JPH09186298A DYNAMIC RAM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH09186298A
公开(公告)日：1997-07-15
申请号：JP35380995
申请日：1995-12-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NARUI SEIJI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , FUJISAWA HIROKI , MIYATAKE SHINICHI , SUZUKI TSUYUKI , AOKI YASUNOBU , TAKAHASHI TSUTOMU , KAJITANI KAZUHIKO
IPC分类号： G11C11/409 , G11C11/407 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize high integration density and a high speed operation without complicating manufacturing processes by providing a voltage converter circuit for limiting the level of the second internal voltage having the predetermined difference for the ground potential of the circuit. SOLUTION: A voltage converter circuit for transmitting an amplified output through level limitation is provided between an input/output node of a sense amplifier SA and complementary bit lines BL, /BL. This voltage converter circuit transmits the amplified output to the corresponding complementary bit lines BL, /BL by limiting the output to the first internal voltage VDL which is lowered as much as the voltage corresponding to the threshold voltage of MOSFET Qm for address selection forming a dynamic memory cell for the high level voltage such as the power supply voltage VCC of the sense amplifier SA and limiting the output to the second internal voltage having the predetermined voltage difference for the low level voltage such as the ground potential VSS of the sense amplifier SA. Thereby, a substrate back bias voltage generating circuit and a voltage booster circuit to form a selection level of the word line can be eliminated.

4. 发明专利

JPH09251783A REFRESH CONTROL METHOD, SEMICONDUCTOR STORAGE DEVICE, AND DATA PROCESSING DEVICE 失效
公开(公告)号：JPH09251783A
公开(公告)日：1997-09-22
申请号：JP5767496
申请日：1996-03-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , SUZUKI TSUKOU , AOKI YASUNOBU , NARUI SEIJI
IPC分类号： G11C11/406 , G11C11/22 , G11C14/00
摘要： PROBLEM TO BE SOLVED: To shorten a refreshing operation time in a dynamic operation mode of a shadow RAM. SOLUTION: This device is provided with a first control means 185 in which refreshing operation of a storage region is stopped and memory access has priority, a storage means 193 which can store a storage region in which refreshing operation is stopped, a second control means 192 for performing the next time memory access for a memory region in which refreshing is stopped with a non-volatile operation mode based on storage information. And when refreshing operation and external memory access conflicts each other, a refreshing time is made apparently zero by making external memory access have priority.

5. 发明专利

JPH09245489A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09245489A
公开(公告)日：1997-09-19
申请号：JP8086596
申请日：1996-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , KAJITANI KAZUHIKO , NARUI SEIJI , SUZUKI TSUKOU , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric memory of a shadow RAM or the like which improves an operation margin checking increase in cost. SOLUTION: First switching means N8-NB are arranged to make a selective connection between non-inversion and inversion signal lines of complementary bit lines BLO*-BLn* of a memory array ARYL, for instance, to be selectively turned ON and made active during the reading operation in a recall mode of a non-volatile mode and non-inversion and inversion signal lines of corresponding complementary bit lines BS0*-BSn* of other memory arrays ARYR kept non-active. The first switching means is turned OFF immediately before the operation of a sense amplifier SA. At the same time, the means concurrently serves as shared MOSFET when a shadow RAM employs a shared sense system.

6. 发明专利

JPH09245488A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09245488A
公开(公告)日：1997-09-19
申请号：JP8086496
申请日：1996-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , KAJITANI KAZUHIKO , NARUI SEIJI , SUZUKI TSUKOU , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To achieve higher reliability of a ferrolectric memory by preventing the deviation and degrading of information holding characteristic of a ferroelectric capacitor as caused by imprinting. SOLUTION: This memory is provided with bit line connection switching circuits SL and SR which respectively contain two pairs of switching MOSFETs N8 and N9 and NA and NB or NC and ND and NE and NF and comprise non-inversion and inversion signal lines in respective complementary bit lines of a memory array ARYL or ARYR and a bit line inversion circuit to allow non-inversion or inversion connection selectively between non-inversion and inversion input/output nodes of a corresponding unit amplification circuit of a sense amplifier SA and a bit line switching state memory circuit to store whether the connection between the complementary bit lines and the unit amplification circuit by the bit line connection switching circuits is in non-inversion or in inversion. Data held of the memory cell are inverted to be rewritten per word line without changing a logic value in substance as each refreshing operation is made.

7. 发明专利

JPH09288894A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09288894A
公开(公告)日：1997-11-04
申请号：JP12239796
申请日：1996-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L21/8246 , H01L27/10 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To make the cycle time of a ferroelectric memory adopting a plate selection system high-speed and to stabilize the reading operation of the ferroelectric memory of large capacity and to reduce power consumption of the memory. SOLUTION: Plate lines VPL0 to VPL7 are made to be effective levels before selection operations of specified word lines are started and the lines are made to be ineffective levels after the word lines are made to be non-selection states. At this time, the effective levels of the plate lines VPL0 to VPL7 are made to be the level of a binary value readout signal in bit lines, that is, the intermediate potential HVC between a power source voltage VCC and a ground potential VSS and the ineffective levels of them are made to be the power source voltage VCC or the ground potential VSS being the precharge potential of the bit lines. Moreover, the memory array of the ferroelectirc memory is divided into plural memory array blocks MAB0 to MAB7 by making complementary bit lines B00* to B0n* or B70* to B7n*, for example, of n+1 pairs a unit and respective array blocks are selectively made to be activated states by making corresponding plate lines VPL0 to VPL7 effective levels like the intermediate potential HVC.

8. 发明专利

JPH09288893A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH09288893A
公开(公告)日：1997-11-04
申请号：JP12239696
申请日：1996-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , NARUI SEIJI , SUZUKI TSUYUKI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , G11C11/404 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To realize ferroelectric memories such as shadow RAM and so forth capable of raising S/N in respective modes simultaneously and also setting its capacitive coupling ratios easily. SOLUTION: At the time of a recall mode, high levels are supplied to electrodes of other sides of capacitors Csa, that is, to plate lines PL0a∼PLma and low levels are supplied to electrodes of other sides of capacitors Csb, that is, to plate lines PL0b∼PLmb and at the time of a read or write mode by a volatile mode, low levels of the same potentials are supplied to these plate lines. Thus, coupling ratios at the time of a recall operation are made large by making capacitors Csb act as load capacitances and at the time of the volatile mode, capacitive coupling ratios at the time of a normal readout operation are made small by making capacitors Csb act as information storage capacitances.

9. 发明专利

JPH09330596A NONVOLATILE MEMORY 失效
公开(公告)号：JPH09330596A
公开(公告)日：1997-12-22
申请号：JP17058796
申请日：1996-06-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , NAGASHIMA YASUSHI , HASEGAWA MASATOSHI , NARUI SEIJI , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption of a nonvolatile memory such as a ferroelectric memory. SOLUTION: A ferroelectric memory has a pair of memory arrays ARYL and ARYR of ferroelectric memory cells of ferroelectric capacitors Cst or Csb and address selecting MOSFETs Qst or Qsb, and sense amplifiers SA provided corresponding to complementary bit lines BL0* (non-inverting, inverting bit lines BL0T, BL0B are attached with '*' at the end. Similarly in the following) to BLn* and BR0* to BRn* of these arrays. In this case, the complementary bit lines are precharged to the same potential Vq or 3Vq as the voltage VPL or VPR supplied to the plates of the Cst and Ssb. For example, the bit line capacities of the lines BR0* to BRn* are used, for example, as dummy capacities for the BL0* to BLn*, and after the selecting operation of the word line is finished, the line BL0* and corresponding BR0*, i.e., dummy capacities are selectively connected, and only the unit amplifier corresponding to the BL0* of the amplifier SA is electively set to the operating state.

10. 发明专利

JPH09245487A FERROELECTIRC MEMORY 失效
公开(公告)号：JPH09245487A
公开(公告)日：1997-09-19
申请号：JP7322596
申请日：1996-03-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJISAWA HIROKI , KAJITANI KAZUHIKO , NARUI SEIJI , SUZUKI TSUKOU , AOKI YASUNOBU
IPC分类号： G11C14/00 , G11C11/22 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To achieve the simplicity of handing with higher reliability by preventing the destruction of information especially in a non-volatile mode of a shadow RAM or the like. SOLUTION: In a shadow RAM or the like selectively usable in a non-volatile mode or in a volatile mode, word lines WLO-WLm and WRO-WRm of memory arrays ARYL and ARYR yet to be selected are forcibly shifted to a selection level VCH to turn ON address selections MOSFETs Q1 and Qb simultaneously or a plate voltage whose potential various just as the potential does in one electrode of ferroelectric capacitors Ct and Cb of the memory cell made yet to be selected is generated and supplied to a ferroelectirc memory cell of the unselected memory arrays ARYL and ARYR so that the potential is made equal between the one electrode and the other between the ferroelectirc capacitors Ct and Cb of the memory yet to be selected. Thus, an electric field is reduced almost to zero as applied to interelectrode films of the ferroelectirc capacitors Ct and Cb of the memory cell thereby preventing destruction of information of the memory cell in the non-volatile mode.

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