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1. 发明专利

DE10334101A1 Semiconductor storage device used as a DRAM device comprises a cell transistor structure with word lines having an n-diffusion layer with an n-carrier concentration which is higher on the region close to the word line of one cell 未知
公开(公告)号：DE10334101A1
公开(公告)日：2004-02-26
申请号：DE10334101
申请日：2003-07-25
申请人： ELPIDA MEMORY INC , HITACHI ULSI SYSTEMS CO , HITACHI LTD
发明人： OYU KIYONORI , OGISHIMA ATSUSHI , UCHIYAMA HIROYUKI , KAWAKITA KEIZO , SUZUKI MASAHITO
IPC分类号： H01L21/76 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108
摘要： Semiconductor storage device comprises a cell transistor structure with word lines (2,3,4,5) having an n-diffusion layer (6, 7, 8) with an n-carrier concentration which is higher on the region close to the word line of one cell than on the region close to the word line of another cell. Independent claims are also included for: (a) alternative semiconductor storage devices; and (b) processes for the production of the semiconductor storage device.

2. 发明专利

JP2004119997A Manufacturing method for semiconductor integrated circuit device, and semiconductor integrated circuit device 审中-公开
公开(公告)号：JP2004119997A
公开(公告)日：2004-04-15
申请号：JP2004012761
申请日：2004-01-21
申请人： Hitachi Ltd , Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOSHIHIRO , TADAKI YOSHITAKA , KAWAKITA KEIZO , AOKI HIDEO , KUMAI TOSHIKAZU , SAITO KAZUHIKO , NISHIMURA MICHIO , TANAKA MICHIO , YUHARA KATSUO , NISHIO SHINYA , KAERIYAMA TOSHIYUKI , CHO SEISHIYU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce the bit-line capacity of a semiconductor integrated circuit device having DRAM. SOLUTION: The semiconductor integrated circuit device comprises a capacitor 5 and a bit-line BL, while coating the perimeter of a word line WL with a cap insulating film 7a and a sidewall 7b made of silicon nitride, and DRAM forming connection holes 9b1 and 9a1, in a self-adjusting way that connect semiconductor areas 4b and 4a of memory cell selection MOS-FET4. The cap insulating film 11a and the sidewall 11b, that coat the bit line BL, are made of a material having a dielectric constant lower than that of silicon nitride. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2000332214A SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000332214A
公开(公告)日：2000-11-30
申请号：JP13665799
申请日：1999-05-18
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , ASAKURA HISAO , SEKIGUCHI TOSHIHIRO , TADAKI YOSHITAKA , KAWAKITA KEIZO
IPC分类号： H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To realize high speed operation of a semiconductor integrated circuit device and reduce the area of a semiconductor chip, at the same time. SOLUTION: A silicon nitride film 13, having a high etching selection ratio to a silicon oxide film constituting an interlayer insulating film 17 and an isolation region 6, is formed on an N+ type semiconductor region 14b. Thereby the spread of a hole bottom diameter d2 of a connection hole 21a formed on an N+ type semiconductor region 14b of an N-channel MISFET Qn is restrained, whereas a diameter d1 of a connection hole 21b formed on a P+ type semiconductor region 15b of a P-channel MISFET Qp is made large, and a relatively wide contact area of a first layer wiring with the P+ type semiconductor region 15b is obtained.

4. 发明专利

JP2000216361A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000216361A
公开(公告)日：2000-08-04
申请号：JP1729799
申请日：1999-01-26
申请人： HITACHI LTD
发明人： YAMADA SATORU , KONISHI NOBUHIRO , NAKAMURA YOSHITAKA , KAWAKITA KEIZO , SEKIGUCHI TOSHIHIRO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique which can improve the yield of DRAM. SOLUTION: For a semiconductor integrated circuit device, a polycrystalline silicon film stacked on a hard mask and a polycrystalline silicon film constituting the hard mask are etched back until a TEOS oxide film 15c is exposed, and after a polycrystalline silicon film 24 is embedded in a connection hole 21, a remainder EN left behind etching of the polycrystalline silicon film 24 which constitutes the hard mask adhering to a part of the surface of the TEOS oxide film 15c is removed by polishing the surface of the TEOS oxide film 15c through CMP method, so that a plug 25 without short-circuit failures due to the remainder EN left behind etching is formed.

5. 发明专利

JPH11204753A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11204753A
公开(公告)日：1999-07-30
申请号：JP34882397
申请日：1997-12-18
申请人： HITACHI LTD
发明人： NAKAMURA YOSHITAKA , ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To facilitate boring of connection holes for connecting different wiring layers and burying a conductor film. SOLUTION: At peripheral circuit regions of DRAM, connection holes for electrically connecting a first layer wiring 14 and a second layer wiring 26 are twice bored to form connection holes 17a, 17b, and, after forming the connection holes 17a, 17b, plugs 18a, 25a are formed in the respective connection holes 17a, 17b.

6. 发明专利

JPH1126719A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1126719A
公开(公告)日：1999-01-29
申请号：JP17370097
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASANO ISAMU , KAWAKITA KEIZO , YAMADA SATORU , IMAI AKIRA , NAKAMURA YOSHITAKA
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent such a defect that an insulating film on a sidewall of a groove of a large area formed in a thick insulating film is peeled off. SOLUTION: After a SOG film 57 having a sufficient thickness to fill a groove 55 and a slot 59 formed in a silicon oxide film 53 is deposited, the SOG film 57 is etched back to expose a polycrystalline silicon film 56 for a lower electrode. Then, this polycrystalline silicon film 56 is etched back to leave only the groove 55 and the slot 59. At this point, an upper part of a groove 80 of a large area is covered with a photoresist film 81, thus preventing the SOG film 57 inside of the groove 80 from being etched back.

7. 发明专利

JPH1126717A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1126717A
公开(公告)日：1999-01-29
申请号：JP17336997
申请日：1997-06-30
申请人： HITACHI LTD
发明人： YOSHIDA MAKOTO , KAWAKITA KEIZO , KUMAUCHI TAKAHIRO , YAMADA SATORU , NAKAMURA YOSHITAKA , ASANO ISAMU , TADAKI YOSHITAKA
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To shorten the period for development by forming the lower electrode having a crown structure in consideration of the embedding limit of an upper electrode, the resolution limit of photolithography technology and the minimum processing dimension. SOLUTION: The lower electrode having a crown structure is considered as the lower electrode which does not use a rough-surface conducting film, as the lower electrode which uses the rough-surface conducting film only for an inner film, as the lower electrode which uses the rough-surface conducting film only for an outer wall, and as the lower electrode which uses the rough-surface conducting film for both the inner wall and the outer wall. When the defective operation of an information storing capacitor element caused by the insufficient deposition of the conducting film of the upper electrode is caused by the inner short circuit and the occurrence of the leakage of the stored electric charge caused by the insufficient outer space between the lower electrodes is caused by the outer short circuit, the limited value of the inner short circuit and the limited value of the outer short circuit are obtained by computation. The photo-lithography limits of a concave crown and a convex crown are obtained by computation. The limits are corrected by the minimum processing dimension. The optimum height of the lower electrode and the inner space are indicated with thick solid lines.

8. 发明专利

JPH1126716A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1126716A
公开(公告)日：1999-01-29
申请号：JP17336897
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASAKURA HISAO , ASANO ISAMU , TADAKI YOSHITAKA , KAWAKITA KEIZO , KAJITANI KAZUHIKO , NAKAMURA MASAYUKI , NAGAI AKIRA
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To restrain the flow of an F-N current in a gate insulating film of a MIS transistor constituting a DRAM, and improve the driving capability of a predetermined MIS transistor constituting the DRAM. SOLUTION: A DRAM constituted by a MOSFET Q for memory cell selection and a capacitor C connected in series with the MOSFET Q is provided on a semiconductor substrate 1, and a method of applying a negative bias voltage to a word line when the MOSFET Q for memory cell selection is off is employed. In this case the thickness of a gate insulating film 5i of a MOSFET which includes the MOSFET Q for memory cell selection and requires a relatively high driving voltage is made greater than the thickness of gate insulating films 8i, 10i of MOSFETs Qn, Qp which require a relatively high current driving capability.

9. 发明专利

JPH1126715A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1126715A
公开(公告)日：1999-01-29
申请号：JP17336797
申请日：1997-06-30
申请人： HITACHI LTD
发明人： ASANO ISAMU , KAWAKITA KEIZO , NAKAMURA YOSHITAKA , YAMADA SATORU
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To improve the work precision of a through-hole connecting an upper electrode of an information storage capacitance element arranged on an upper part of a MISFET for memory cell selection and a wiring for power supply, without increasing the chip size. SOLUTION: By depositing, in a peripheral circuit region of a DRAM, a thick silicon oxide film (53) having a thickness equivalent to the height of an information storage capacitance element C of a memory cell, a step between a memory array and the peripheral circuit region is eliminated and a boundary portion between the memory array and the peripheral circuit region is made plane. Through a through-hole 74 formed directly above a slot 55a formed in the plane boundary portion, a third wiring 78 for power supply and an upper electrode of the information storage capacitance element C are electrically connected with each other.

10. 发明专利

JPH09321238A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09321238A
公开(公告)日：1997-12-12
申请号：JP13553496
申请日：1996-05-29
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： SEKIGUCHI TOSHIHIRO , TADAKI YOSHITAKA , KAWAKITA KEIZO , AOKI HIDEO , KUMAI TOSHIKAZU , SAITO KAZUHIKO , NISHIMURA MICHIO , TANAKA MICHIO , YUHARA KATSUO , NISHIO SHINYA , KAERIYAMA TOSHIYUKI , CHIYOU SEISHIYU
IPC分类号： H01L21/8242 , H01L21/60 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce the capacitance of the bit lines of a semiconductor integrated circuit device having DRAM. SOLUTION: The semiconductor integrated circuit device comprises a DRAM having connection holes 9b1, 9b2a, 9b2b and 9a1 self-matchedly formed to connect semiconductor regions 4b, 4a of memory cell selective MOS FETs 4 to bit lines BL and capacitors 5 by covering the periphery of word lines WL with a silicon nitride cap insulation film 7a and side walls 7b. The bit lines BL are covered with a cap insulation film 11a and side walls 11b, each made of a material having a lower dielectric const. than that of the silicon nitride.

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