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1. 发明专利

MY115056A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONNECTING SEMICONDUCTOR REGION AND ELECTRICAL WIRING METAL VIA TITANIUM SILICIDE LAYER AND METHOD OF FABRICATION THEREOF 未知
公开(公告)号：MY115056A
公开(公告)日：2003-03-31
申请号：MYPI9604725
申请日：1996-11-14
申请人： HITACHI LTD
发明人： TODOROBARU HIROMI , UCHIYAMA HIROYUKI , ABE SONOKO , MIURA HIDEO , SUZUKI MASAYUKI , NISHIHARA SHINJI , IKEDA SHUJI , SAHARA MASASHI , ISHIDA SHINICHI , ABE HIROMI , OGISHIMA ATUSHI
IPC分类号： H01L21/28 , H01L21/768 , H01L23/48 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108
摘要： A SEMICONDUCTOR DEVICE COMPRISES A SILICON SUBSTRATE, AN ELECTRICAL WIRING METAL, AN INSULATING FILM FORMED ON THE SILICON SUBSTRATE, A PLURALITY OF CONTACT HOLES FORMED IN THE INSULATING FILM FOR CONNECTING THE SILICON SUBSTRATE AND THE ELECTRICAL WIRING METAL TO EACH OTHER, AND A TITANIUM SILICIDE FILM FORMED IN THE CONTACT HOLES. THE THICKNESS OF THE TITANIUM SILICIDE FILM IS 10 NM TO 120 NM, OR PREFERABLY, 20 NM TO 84 NM. SEMICONDUCTOR REGIONS AND THE ELECTRICAL WIRING METAL ARE CONNECTED TO EACH OTHER THROUGH THE TITANIUM SILICIDE FILM.

2. 发明专利

AU1940597A Process for producing semiconductor integrated circuit device 未知
公开(公告)号：AU1940597A
公开(公告)日：1998-10-12
申请号：AU1940597
申请日：1997-03-14
申请人： HITACHI LTD
发明人： NISHIHARA SHINJI , IKEDA SHUJI , HASHIMOTO NAOTAKA , MOMIJI HIROSHI , ABE HIROMI , FUKADA SHINICHI , SUZUKI MASAYUKI
IPC分类号： H01L23/532 , H01L29/45 , H01L29/49 , H01L21/28 , H01L29/78

3. 发明专利

SG47193A1 Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof 未知
公开(公告)号：SG47193A1
公开(公告)日：1998-03-20
申请号：SG1996011097
申请日：1996-11-13
申请人： HITACHI LTD
发明人： TODOROBARU HIROMI , MIURA HIDEO , SUZUKI MASAYUKI , NISHIHARA SHINJI , IKEDA SHUJI , SAHARA MASASHI , ISHIDA SHINICHI , ABE HIROMI , OGISHIMA ATUSHI , UCHIYAMA HIROYUKI , ABE NEE TODA SONOKO
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/485 , H01L21/28 , H01L23/522 , H01L27/108
摘要： A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

4. 发明专利

JP2001223180A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001223180A
公开(公告)日：2001-08-17
申请号：JP2001007146
申请日：2001-01-16
申请人： HITACHI LTD
发明人： GOHARA HIROMI , MIURA HIDEO , SUZUKI MASAYASU , NISHIHARA SHINJI , IKEDA SHUJI
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device wherein contact of low resistance is obtained without generating disconnection on a connection interface between silicon and a titanium silicide film in a contact hole, and a manufacturing method of the device. SOLUTION: A semiconductor device is connected via the titanium silicide film 6 at the inside or a bottom part of the contact hole 5 wherein a single crystal silicon substrate 1 on which metal 13 for electric wiring and a semiconductor element are formed or polycrystalline silicon 10 is formed in an insulating film. In this semiconductor device, thickness of the titanium silicide film is set at least 20 nm and at most 75 nm.

5. 发明专利

JP2001196548A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001196548A
公开(公告)日：2001-07-19
申请号：JP2000010107
申请日：2000-01-14
申请人： HITACHI LTD
发明人： IWASAKI TOMIO , MIURA HIDEO , NAKAJIMA TAKASHI , OTA HIROYUKI , NISHIHARA SHINJI , SAWARA MASASHI
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L23/532 , H01L27/108 , H01L27/10
摘要： PROBLEM TO BE SOLVED: To solve problems such as discontinued tungsten wiring and decrease in reliability and yields. SOLUTION: This semiconductor device has a capacitor. In the capacitor, a first electrode 15, an oxide film 16 that comes into contact with the first electrode and has high permitivity or ferroelectricity, and a second electrode 17 that comes into contact with the oxide film are formed in this order at one main surface side of a silicon substrate 1, where a metal wiring layer is formed. In this case, the material of the metal wiring layer is tungsten, in which molybdenum is added.

6. 发明专利

JPH11340144A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH11340144A
公开(公告)日：1999-12-10
申请号：JP14080098
申请日：1998-05-22
申请人： HITACHI LTD
发明人： NAKAJIMA TAKASHI , MIURA HIDEO , YAJIMA AKIRA , KOBAYASHI HIDE , NISHIHARA SHINJI , UCHIDA JUNICHI
IPC分类号： C23C4/00 , C23C4/04 , H01L21/203 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of foreign matters from the surface of a deposition preventing jig while a film is formed on the surface of a semiconductor substrate and, at the same time, to reduce the exchanging frequency of the adhesion preventing jig by forming irregularities having specific heights on the surface of a melt-sprayed film and another irregularities having specific height on the interface of the melt-sprayed film. SOLUTION: The melt-sprayed film 11 coating the surface of the deposition preventing jig 4 is composed of a first melt-sprayed film 11a on the jig 4 side and a second melt-sprayed film 11b laminated upon the film 11a. On the surface of the film 11b, the irregularities 20 having heights of 30-500 μm are formed. In addition, on the interface between the first and second melt-sprayed films 11a and 11b, recessing and protrusions 21 having heights of 30-500 μm are formed. Therefore, the film 11 can be formed well by suppressing the production of foreign matters. In addition, a stable semiconductor device manufacturing method can be provided by stably operating a film forming device, such as the sputtering system, etc. Moreover, a highly reliable semiconductor device can be provided at a low cost.

7. 发明专利

JPH07278807A SPUTTERING TARGET ASSEMBLY 失效
公开(公告)号：JPH07278807A
公开(公告)日：1995-10-24
申请号：JP8909694
申请日：1994-04-04
申请人： JAPAN ENERGY CORP , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ANAMI JUNICHI , KANANO OSAMU , YAMAMOTO MASASHI , NISHIHARA SHINJI , ABE TOSHIHIKO , YOSHIURA AIMEI
IPC分类号： C23C14/34
摘要： PURPOSE:To obtain a target assembly which has uniform cooling effect and uniform film quality and is excellent in consumption characteristic by joining a target to a backing plate made of annealed copper with low strength. CONSTITUTION:A planar target 9 made of WSi, etc., is joined to the backing plate 10 and the obtained sputtering target assembly 13 is set on a cooling part 7 and then magnetron sputtering coating is executed thereon. The backing plate 10 is made of annealed copper in which at least surface part material has , preferably tensile strength. In such a manner, adhesion between the assembly 13 and the cooling part 7 is improved, further both parts are excellent in heat conductivity and consequently, cooling effect thereof is remarkably improved and consumption of the target material is uniformized to obtain uniform film quality. Further, when an annular target having a side-wall is used, the backing plate at the side-wall part is unnecessary by using this backing plate.

8. 发明专利

JPH07142475A FORMATION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH07142475A
公开(公告)日：1995-06-02
申请号：JP14731593
申请日：1993-06-18
申请人： HITACHI LTD
发明人： KAWABUCHI YASUSHI , TANIGAKI YUKIO , HARUTA AKIRA , SUZUKI MASAYASU , NISHIHARA SHINJI , ISHIDA SHINICHI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To enhance the flatness of a semiconductor integrated circuit device along with electrical reliability thereof. CONSTITUTION:The method for forming a semiconductor integrated circuit device having a wiring 11 formed by sequentially laminating a polysilicon film 11A and a high melting point metal silicide film 11C on the main plane of a semiconductor substrate 1 comprises a step for depositing the polysilicon film 11A and the high melting point metal film 11B sequentially on the main plane of the semiconductor substrate 1, and a step for sequentially patterning the polysilicon film 11A and the high melting point metal film 11B to form a laminate wiring 11. The method further comprises a step for subjecting the semiconductor substrate 1 to heat treatment thus depositing a high melting point metal silicide film 11C at the interface region between both films 11A and 11B, and a step for subjecting the laminate wiring 11 to selective etching thus removing the high melting point metal film 11B.

9. 发明专利

JPH06349771A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06349771A
公开(公告)日：1994-12-22
申请号：JP14103293
申请日：1993-06-14
申请人： HITACHI LTD
发明人： SUZUKI MASAYASU , HARUTA AKIRA , NISHIHARA SHINJI , ISHIDA SHINICHI , TANIGAKI YUKIO
IPC分类号： H01L21/28 , C23C18/31 , H01L21/288 , H01L21/336 , H01L21/768 , H01L23/522 , H01L29/78 , H01L21/90 , H01L29/784
摘要： PURPOSE:To reduce the diffused layer resistance and the contact hole resistance of a semiconductor integrated circuit device without deteriorating its reliability. CONSTITUTION:A first metal silicide layer 5a which is made of silicide of alloy of one of Ti, Zr and Hf and one of W and Mo is provided over the whole surface of a diffused layer 5 which is formed on the main surface of a semiconductor substrate 1 and of which an n-type channel MOS-FET 4 is composed. A metal film 9 which is formed by a selective CVD method or a plating method is buried in a contact hole 12 which connects the silicide layer 5a to a first layer wiring 11.

10. 发明专利

JPH05175346A WIRING AND ITS FORMING METHOD 失效
公开(公告)号：JPH05175346A
公开(公告)日：1993-07-13
申请号：JP34270291
申请日：1991-12-25
申请人： HITACHI LTD
发明人： HARUTA AKIRA , NISHIHARA SHINJI , TANIGAKI YUKIO , KATO TOKIO , SUZUKI MASAYASU
IPC分类号： H01L21/205 , H01L21/3205 , H01L21/768 , H01L23/52
摘要： PURPOSE:To reduce the contact resistance between a W wiring and a diffusion layer and to improve the characteristics in a semiconductor device with the W wiring. CONSTITUTION:After opening a contact hole 4 for connecting a W wiring 7 and a diffusion layer 2, a Ti W film is formed, heat treatment is performed at 600-750 deg.C, and then the W wiring 7 is formed, thus forming a three-element alloy (TiW) Si layer 6 of Ti, W, and Si between the W wiring 7 and the diffusion layer 2. Therefore, in a semiconductor device with the W wiring 7, the contact resistance of the W wiring 7 and the diffusion layer 2 can reduced and the response speed of the semiconductor device can be improved.

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