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1. 发明专利

DE112008000800B4 Dreidimensionale Kreuzschienenarray-Systeme und Verfahren zum Schreiben von Informationen zu dreidimensionalen Kreuzschienenarray-Übergängen und Lesen von in denselben gespeicherten Informationen 未知
公开(公告)号：DE112008000800B4
公开(公告)日：2016-01-28
申请号：DE112008000800
申请日：2008-03-21
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： WU WEI , WILLIAMS STANLEY R , ROBINETT WARREN , SNIDER GREGORY , YU ZHAONING , WANG SHIH-YUAN , STEWART DUNCAN
IPC分类号： G11C5/06 , B82Y10/00 , G11C13/00 , H01L27/10
摘要： Ein konfigurierbares dreidimensionales Kreuzschienenarraysystem (1000, 1100), das folgende Merkmale aufweist: eine Mehrzahl von Kreuzschienenarrays (1002–1004, 1102–1104), wobei jedes Kreuzschienenarray eine erste Schicht von Nanodrähten (702–704), eine zweite Schicht von Nanodrähten (706–708), die die erste Schicht von Nanodrähten überlagert, eine dritte Schicht von Nanodrähten (710–712), die die zweite Schicht von Nanodrähten überlagert, und einen Kreuzschienenübergang (810) umfasst, der an einem Schnittpunkt von drei sich überlagernden Nanodrähten positioniert ist; einen ersten Demultiplexer (1006, 1106), der konfiguriert ist, um zumindest einen Abschnitt der Nanodrähte in der ersten Schicht von Nanodrähten jedes Kreuzschienenarrays zu adressieren; einen zweiten Demultiplexer (1008, 1108), der konfiguriert ist, um zumindest einen Abschnitt der Nanodrähte in der zweiten Schicht von Nanodrähten jedes Kreuzschienenarrays zu adressieren; und einen dritten Demultiplexer (1010, 1110), der konfiguriert ist, um ein Signal an zumindest einen Abschnitt der Nanodrähte in der dritten Schicht von Nanodrähten jedes Kreuzschienenarrays zu liefern.

2. 发明专利

DE602007005156D1 未知
公开(公告)号：DE602007005156D1
公开(公告)日：2010-04-15
申请号：DE602007005156
申请日：2007-10-16
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： ROBINETT WARREN , KUEKES PHILIP J
IPC分类号： G11C13/02
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

3. 发明专利

AT459963T 未知
公开(公告)号：AT459963T
公开(公告)日：2010-03-15
申请号：AT07852786
申请日：2007-10-16
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： ROBINETT WARREN , KUEKES PHILIP J
IPC分类号： G11C13/02
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

4. 发明专利

DE112008000800T5 rfahren zum Schreiben von Informationen zu dreidimensionalen Kreuzschienenarray-Übergängen und Lesen von in denselben gespeicherten Informationen 未知
公开(公告)号：DE112008000800T5
公开(公告)日：2010-07-01
申请号：DE112008000800
申请日：2008-03-21
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： WU WEI , WILLIAMS STANLEY R , ROBINETT WARREN , SNIDER GREGORY , YU ZHAONING , WANG SHIH-YUAN , STEWART DUNCAN
IPC分类号： G11C5/06 , H01L27/10

5. 发明申请

WO2008008419A3 DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING 审中-公开
标题翻译：使用系列复制和错误控制编码的缺陷和失败的解复用器
公开(公告)号：WO2008008419A3
公开(公告)日：2008-09-25
申请号：PCT/US2007015861
申请日：2007-07-11
申请人： HEWLETT PACKARD DEVELOPMENT CO , ROBINETT WARREN , KUEKES PHILIP J , WILLIAMS STANLEY R
发明人： ROBINETT WARREN , KUEKES PHILIP J , WILLIAMS STANLEY R
IPC分类号： G06F11/10 , H03K19/177
CPC分类号： H03K19/007 , G06F11/1076 , H03K19/00315
摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers (figures 14 an 16). This method is applicable to nanoscale, microscal, or larger-scale demultiplexer circuits,. Demultiplexer circuits can be viewed as a set of AND gates (figures 9A-B), each including a reversibly switchable interconnection between a number of address lines (910-912 and 920-922), or address-line-derived signal lines, and an output signal line (914 and 924). Each reversibly switchable interconnection includes one ot more reversibly switchable elements (906-908 and 916-918). In certain demultiplexer embodiments, NMOS (102) and/or PMOS transistors (206) are employed as reversibly switchable elements. In the method that representd one embodiment of the present invention, two or more serially connected transistors (410, 412, and 411, 413; 1502) are employed in each reversibly switchable interconnection, so that short defects in up to one less then the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines (1602, 1604) and additional switchable interconnections (1610) so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.
摘要翻译：本发明的一个实施例是用于构造缺陷和容错解复用器的方法（图14和16）。该方法适用于纳米级，微型或大规模解复用器电路。解复用器电路可以被看作是一组与门（图9A-B），每一个包括多个地址线（910-912和920-922）之间的可逆切换互连或地址线导出的信号线，以及输出信号线（914和924）。每个可逆切换互连包括一个或多个可逆切换元件（906-908和916-918）。在某些解复用器实施例中，NMOS（102）和/或PMOS晶体管（206）被用作可逆切换元件。在代表本发明的一个实施例的方法中，在每个可逆切换的互连中使用两个或更多个串联的晶体管（410,412和411,413; 1502），使得短到少于1个串联互连的晶体管不会导致可逆切换互连的故障。另外，误差控制编码技术被用于引入额外的地址线导出的信号线（1602,1604）和附加的可切换互连（1610），使得即使当多个单独的可切换互连打开时，解复用器也可以起作用缺陷型。

6. 发明申请

WO2008048597A3 CROSSBAR-MEMORY SYSTEMS WITH NANOWIRE CROSSBAR JUNCTIONS 审中-公开
标题翻译：具有NANOWIRE CROSSBAR JUNCTIONS的交叉记忆体系统
公开(公告)号：WO2008048597A3
公开(公告)日：2008-06-19
申请号：PCT/US2007022070
申请日：2007-10-16
申请人： HEWLETT PACKARD DEVELOPMENT CO , ROBINETT WARREN , KUEKES PHILIP J
发明人： ROBINETT WARREN , KUEKES PHILIP J
IPC分类号： G11C13/02
CPC分类号： G11C13/02 , B82Y10/00 , G06F11/1008 , G06F11/1076 , G11C11/54 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2013/009 , G11C2213/16 , G11C2213/77 , G11C2213/81
摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system (800) comprises a first layer of microscale signal lines (808), a second layer of microscale signal lines '(810), a first layer of nanowires (804) configured so that each first layer, nanowire overlaps each first layer microscale signal line (808), and a second layer of nanowires (806) configured so that each second layer nanowire overlaps each second layer microscale signal line (810) and overlaps each first layer nanowire (804). The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires (804) to first layer microscale signal lines (808) and to selectively connect second layer nanowires (806) to second layer microscale signal lines (810). The crossbar-memory system (800) also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire. at each crossbar intersection.
摘要翻译：本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。在本发明的一个实施例中，交叉开关存储器系统（800）包括第一层微米信号线（808），第二层微米信号线（810），第一层纳米线（804）每个第一层纳米线与每个第一层微米信号线（808）重叠，以及第二纳米线层（806），其被配置为使得每个第二层纳米线与每个第二层微米信号线（810）重叠并与每个第一层纳米线 804）。交叉开关存储器系统包括被配置为选择性地将第一层纳米线（804）连接到第一层微型信号线（808）并且选择性地将第二层纳米线（806）连接到第二层微量信号线（810）的非线性隧道电阻器。交叉开关存储器系统（800）还包括被配置为将每个第一层纳米线连接到每个第二层纳米线的非线性隧道 - 迟滞电阻器。在每个交叉口交叉点。

7. 发明申请

WO2007089802A2 TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS 审中-公开
标题翻译：基于隧穿 - 电阻 - 结点的微型/纳米级解复用器阵列
公开(公告)号：WO2007089802A2
公开(公告)日：2007-08-09
申请号：PCT/US2007002577
申请日：2007-01-30
申请人： HEWLETT PACKARD DEVELOPMENT CO , ROBINETT WARREN , SNIDER GREGORY S , STEWART DUNCAN , STRAZNICKY JOSEPH
发明人： ROBINETT WARREN , SNIDER GREGORY S , STEWART DUNCAN , STRAZNICKY JOSEPH
CPC分类号： G11C8/10 , G11C13/0023 , H03M13/51
摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodimentof the present invention, an encoder-demulriplexer comprises a number of input signal lines and an encoder (1304) that generates an n-bit-constant-weight-code code-word internal address (1320, 1506, 1704) for each different input address (1318, 1702) received on the input signal lines. The encoder-demultiplexer also includes n microscale signal lines (1306-1311) on which an n-bit-constant-weight-code code word internal address is out put by the encoder and a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with then microscale signal lines (1306-1311) via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal adress (1320, 1506, 1704).
摘要翻译：本发明的各种实施例涉及包括隧道电阻器纳米线结的解复用器，并且涉及用于在纳米级和混合尺度解复用器中可靠地寻址纳米线信号线的纳米线寻址方法。在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和编码器（1304），编码器（1304）为每个输入信号线生成n位恒定加权码字内部地址（1320,1506,1704）在输入信号线上接收不同的输入地址（1318,1702）。编码器 - 解复用器还包括n个微型信号线（1306-1311），编码器输出n位恒定加权码字内部地址，并且编码器 - 解复用器寻址的纳米线信号线互连与经由隧道电阻器结的微米级信号线（1306-1311）相连，所述编码器 - 解复用器寻址的纳米线信号线均与n位恒定重量码码字内部地址（1320,1506,1704）相关联。

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