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    • 7. 发明授权
    • Lateral cache-to-cache cast-in
    • 横向缓存到缓存投入
    • US08225045B2
    • 2012-07-17
    • US12335975
    • 2008-12-16
    • Guy L. GuthrieAlvan W. NgMichael S. SiegelWilliam J. StarkeDerek E. WilliamsPhillip G. Williams
    • Guy L. GuthrieAlvan W. NgMichael S. SiegelWilliam J. StarkeDerek E. WilliamsPhillip G. Williams
    • G06F12/00
    • G06F12/0811G06F12/0804G06F12/0831G06F12/0862
    • A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
    • 数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。 第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存,并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。 响应于数据请求,选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。 第一处理单元在互连结构上发出横向聚合(LCO)命令,该命令标识要从第一较低级缓存中抛出的受害缓存行,并且指示较低级缓存是预期目的地。 响应于指示LCO命令的成功的一致性响应,从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。
    • 8. 发明授权
    • Updating partial cache lines in a data processing system
    • 更新数据处理系统中的部分缓存行
    • US08117390B2
    • 2012-02-14
    • US12424434
    • 2009-04-15
    • David W. CummingsGuy L. GuthrieHugh ShenWilliam J. StarkeDerek E. WilliamsPhillip G. Williams
    • David W. CummingsGuy L. GuthrieHugh ShenWilliam J. StarkeDerek E. WilliamsPhillip G. Williams
    • G06F13/00
    • G06F12/0822G06F12/0897G06F2212/507
    • A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
    • 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应,较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求,而不缓存部分高速缓存行。