专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5862070A Discrete cosine transformation circuit 失效
标题翻译：离散余弦变换电路
公开(公告)号：US5862070A
公开(公告)日：1999-01-19
申请号：US820002
申请日：1997-03-18
申请人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
发明人： Guoliang Shou , Jie Chen , Chanming Zhou , Sunao Takatori
IPC分类号： G06F17/14 , G06G7/22 , G06G7/02 , G06G7/19
CPC分类号： G06G7/22 , G06F17/147
摘要： A high-speed discrete cosine transformation circuit includes the one-dimensional input signals x(0) to x(7) being input in parallel to the positive input terminals "+" or the negative input terminals "-" of eight neural operation units (NOU) 11 to 18 through capacitors d0 to d6. In each NOU 11 to 18, input signals x(0) to x(7) are added and subtracted. Input signals x(0) to x(7) are multiplied beforehand by the coefficient in proportion to the capacities of capacitors d0 to d6 which are connected to NOU 11 to 18. Thereafter, discrete cosine transforming coefficients y(0) to y(7) are output. A two-dimensional discrete cosine transformation circuit is realized by using the one-dimensional discrete cosine transforming circuit.
摘要翻译：高速离散余弦变换电路包括与八个神经运算单元的正输入端子“+”或负输入端子“ - ”并联输入的一维输入信号x（0）〜x（7） NOU）11至18通过电容器d0至d6。在每个NOU 11至18中，输入信号x（0）至x（7）被加和减。输入信号x（0）至x（7）预先乘以与连接到NOU 11至18的电容器d0至d6的电容成比例的系数。之后，离散余弦变换系数y（0）至y（7 ）被输出。通过使用一维离散余弦变换电路实现二维离散余弦变换电路。

2. 再颁专利

USRE37953E1 Filter circuit for communication 失效
标题翻译：滤波电路进行通讯
公开(公告)号：USRE37953E1
公开(公告)日：2002-12-31
申请号：US09404783
申请日：1999-09-24
申请人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： G06G702
CPC分类号： H03H17/0254 , H03H11/04 , H04B1/7093
摘要： The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.
摘要翻译：本发明的目的是提供一种用于通信生成有效数字输出的滤波器电路以及低功耗滤波电路中的模拟输出。根据通过在采集之后对信号进行部分采样可以执行峰值检测的经验，间歇地保持模拟输出信号，使A / D转换电路的功能速度最小化。

3. 发明授权

US5974038A Receiver for code division multiple access communication system 失效
标题翻译：接收机用于码分多址通信系统
公开(公告)号：US5974038A
公开(公告)日：1999-10-26
申请号：US864784
申请日：1997-05-29
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04B1/707 , H04B1/7075 , H04B1/7093 , H04B1/7115 , H04L7/00 , H04B7/216
CPC分类号： H04B1/708 , H04B1/7093 , H04B1/7115 , H04B2201/70709
摘要： This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.
摘要翻译：本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号。此外，进行解扩。来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

4. 发明授权

US5930290A Spread spectrum communications system for high-speed communications 失效
标题翻译：扩频通信系统，用于高速通信
公开(公告)号：US5930290A
公开(公告)日：1999-07-27
申请号：US841217
申请日：1997-04-30
申请人： Changming Zhou , Guoliang Shou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Kenzo Urabe
发明人： Changming Zhou , Guoliang Shou , Xuping Zhou , Makoto Yamamoto , Sunao Takatori , Kenzo Urabe
IPC分类号： H04B1/707 , H04B1/7093 , H04J13/10 , H04B15/00 , H04B7/216
CPC分类号： H04J13/0077 , H04B1/7093
摘要： A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.
摘要翻译：提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。要发送的一系列数字数据被分为4位帧。每帧的4位数据按预定顺序分成第一至第四元素。第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。要传输的数据的频谱通过乘以这些复数来传播。四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。根据匹配滤波器的输出，恢复第一至第四元件。

5. 发明授权

US5872466A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5872466A
公开(公告)日：1999-02-16
申请号：US686950
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03H11/04 , H03H17/02 , H04B1/707 , H04B1/7093 , H04L7/00 , H04L7/10 , H03K5/00
CPC分类号： H03H11/04 , H03H17/0254
摘要： A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.
摘要翻译：公开了具有降低的电力消耗的匹配滤波器。由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。各组中的信号通过电容耦合并联并且在电路中间歇地供电。

6. 发明授权

US5783961A Inverted amplifying circuit 失效
标题翻译：反相放大电路
公开(公告)号：US5783961A
公开(公告)日：1998-07-21
申请号：US764637
申请日：1996-12-11
申请人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03K19/0948 , H03F1/02 , H03F1/34 , H03F3/46 , H03F3/72 , H03K5/153 , H03H11/26
CPC分类号： H03F3/72
摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.
摘要翻译：本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。当反相放大电路不工作时，MOS开关打开。

7. 发明授权

US5734583A Capacitance forming method 失效
标题翻译：电容成型法
公开(公告)号：US5734583A
公开(公告)日：1998-03-31
申请号：US536326
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H01L27/08 , H01L27/10 , G06F17/50
CPC分类号： H01L27/0805 , H01L27/101
摘要： A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.
摘要翻译：用于在大规模集成电路（LSI）内形成对应于多个常数的电容的电容形成方法包括以预定形状定义单位电容的步骤，限定多个单位电容的排列，在LSI的区域中形成二维电容的总容量，选择与要形成的电容的容量之间的最大容量相对应的数字的单位电容，使得所选择的单位电容等效地分散在该区域上，并且依次选择电容量以及容量顺序的最大容量的电容量，并且选择与所选择的每个电容的容量对应的数量的单位电容，使得所选择的单位电容等价地分散在其余单位电容尚未选择。

8. 发明授权

US5666080A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US5666080A
公开(公告)日：1997-09-09
申请号：US262059
申请日：1994-06-17
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/063 , G11C27/02 , G06G7/42 , H03K17/62
CPC分类号： G11C27/024 , G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/0635
摘要： Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction is performed by to MOSs of anti-polarity inputted analog input voltages to gates.
摘要翻译：通过电容耦合或电阻耦合进行加法。量化电路由接收模拟输入电压的多个阈值电路实现。通过反向极性输入的模拟输入电压MOS到门执行减法。

9. 发明授权

US5617053A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US5617053A
公开(公告)日：1997-04-01
申请号：US468762
申请日：1995-06-06
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/063 , G11C27/02 , G06G7/16
CPC分类号： G06G7/14 , G06G7/06 , G06G7/26 , G06J1/00 , G06N3/0635 , G11C27/026
摘要： A computational circuit that includes a first capacitive coupling that connects a plurality of analog input voltages to a first inverter. The first inverter is connected to a second inverter through a connecting capacitance. A first feedback capacitance connects the output of the first inverter to its input, and a second feedback capacitance connects the output of the second inverter to its input. A first additional capacitance is operatively connected between ground and the first capacitive coupling, and a second additional capacitance is connected between ground and the connecting capacitance. The values of the first and second additional capacitances is selected such that the closed-loop gains of the first and second inverters are substantially equal.
摘要翻译：一种计算电路，包括将多个模拟输入电压连接到第一反相器的第一电容耦合。第一反相器通过连接电容连接到第二反相器。第一反馈电容将第一反相器的输出连接到其输入，第二反馈电容将第二反相器的输出连接到其输入。第一附加电容可操作地连接在地和第一电容耦合之间，第二附加电容连接在地和连接电容之间。选择第一和第二附加电容的值使得第一和第二反相器的闭环增益基本相等。

10. 发明授权

US5563544A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US5563544A
公开(公告)日：1996-10-08
申请号：US487154
申请日：1995-06-07
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/063 , G11C27/02
CPC分类号： G11C27/024 , G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/0635
摘要： A comparator circuit in an analog computational device includes a complement circuit that receives a first analog input. The complement circuit outputs a quantized complement of the first input to first and second addition circuits. A second analog input is also provided to the first and second addition circuits. The first and second addition circuits add the complement circuit output to the second analog input and provide a low output if the result of the addition exceeds threshold values set for the first and second addition circuits. The outputs of the first and second addition circuits are provided to a judging circuit to determine which is greater.
摘要翻译：模拟计算装置中的比较器电路包括接收第一模拟输入的补码电路。补码电路将第一输入的量化补码输出到第一和第二加法电路。还向第一和第二加法电路提供第二模拟输入。第一和第二加法电路将补码电路输出添加到第二模拟输入，并且如果相加的结果超过为第一和第二加法电路设置的阈值，则提供低输出。第一加法电路和第二加法电路的输出被提供给判断电路以确定哪一个更大。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式