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1. 发明授权

US06563373B1 Filter circuit utilizing a plurality of sampling and holding circuits 有权
标题翻译：利用多个取样和保持电路的滤波电路
公开(公告)号：US06563373B1
公开(公告)日：2003-05-13
申请号：US09165301
申请日：1998-10-02
申请人： Guoliang Shou , Kunihiko Suzuki , Changming Zhou
发明人： Guoliang Shou , Kunihiko Suzuki , Changming Zhou
IPC分类号： H03H1502
CPC分类号： H04B1/7093 , H03H11/04
摘要： An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.
摘要翻译：滤波器电路中的模拟计算电路通过从已知输入和已知乘数的计算结果估计误差来校正计算误差。根据估计的误差改变乘数。滤波电路在输入侧具有电压 - 电流转换器，在输出侧具有电流 - 电压转换器，并且在其中执行电流计算。

2. 再颁专利

USRE37953E1 Filter circuit for communication 失效
标题翻译：滤波电路进行通讯
公开(公告)号：USRE37953E1
公开(公告)日：2002-12-31
申请号：US09404783
申请日：1999-09-24
申请人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Chanming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： G06G702
CPC分类号： H03H17/0254 , H03H11/04 , H04B1/7093
摘要： The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.
摘要翻译：本发明的目的是提供一种用于通信生成有效数字输出的滤波器电路以及低功耗滤波电路中的模拟输出。根据通过在采集之后对信号进行部分采样可以执行峰值检测的经验，间歇地保持模拟输出信号，使A / D转换电路的功能速度最小化。

3. 发明授权

US06281831B1 Analog to digital converter 失效
标题翻译：模数转换器
公开(公告)号：US06281831B1
公开(公告)日：2001-08-28
申请号：US09075342
申请日：1998-05-11
申请人： Guoliang Shou , Ying Chen , Takashi Tomatsu
发明人： Guoliang Shou , Ying Chen , Takashi Tomatsu
IPC分类号： H03M136
CPC分类号： H03M1/42
摘要： An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding circuits have thresholds equal to a weights of the bits. The inverters of the last stage are of thresholds different from those of the first stage.
摘要翻译： A / D转换器具有对应于输出数字数据的位的多个阈值电路，每个阈值电路包括从第一阶段到最后阶段串行连接的奇数个反相器。阈值电路的第一级反相器具有等于位的权重的阈值。最后阶段的逆变器的阈值与第一级的阈值不同。

4. 发明授权

US6038250A Initial synchronization method and receiver for DS-CDMA inter base station asynchronous cellular system 失效
标题翻译：用于DS-CDMA基站间异步蜂窝系统的初始同步方法和接收机
公开(公告)号：US6038250A
公开(公告)日：2000-03-14
申请号：US3509
申请日：1998-01-06
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou
IPC分类号： H04B1/707 , H04B1/7075 , H04B7/26 , H04W56/00 , H04W76/02 , H04B7/216
CPC分类号： H04B1/7077 , H04B1/7083 , H04B1/70735 , H04B1/70751 , H04B2201/70702
摘要： Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.
摘要翻译：使用初始同步方法和用于DS-CDMA基站间异步蜂窝系统的接收机以高速搜索小区。基带接收信号被输入到匹配滤波器，并与从扩展码发生器提供的扩展码相关。信号电力计算器计算匹配滤波器的相关输出的功率，并将结果输出到长码同步定时确定器，阈值计算器和长码标识符。在初始小区搜索期间，扩频码发生器输出每个基站的控制信道共同的短码＃0。在确定了长代码同步定时之后，构成从每个基站唯一的长码#i合成的合成扩展码序列的一部分的N个码片的每个片段和短码＃0 顺序更换并输出。

5. 发明授权

US5959875A Analog signal characterizer for functional transformation 失效
标题翻译：用于功能转换的模拟信号表征器
公开(公告)号：US5959875A
公开(公告)日：1999-09-28
申请号：US812650
申请日：1997-03-07
申请人： Nobuaki Kawahara , Kenzo Urabe , Changming Zhou , Guoliang Shou
发明人： Nobuaki Kawahara , Kenzo Urabe , Changming Zhou , Guoliang Shou
IPC分类号： G06G7/19
CPC分类号： G06G7/1921
摘要： A signal characterizer for performing functional transformations such as Fast Fourier Transforms (FFTs), which converts an input serial analog signal into a plurality of parallel discrete signals using an analog-type serial-to-parallel converter. The discrete signals are then supplied to the input terminals of butterfly operation circuits to process the parallel discrete signals into a plurality of transformed signals. A switch supplies the transformed signals to a serial signal output terminal. The switch is controlled by a controller so that the input signal sequence is converted to a serial signal sequence according to a predetermined order.
摘要翻译：一种用于执行诸如快速傅立叶变换（FFT）的功能变换的信号表征器，其使用模拟型串并转换器将输入的串行模拟信号转换为多个并行离散信号。然后将离散信号提供给蝶形运算电路的输入端，以将并行离散信号处理成多个变换信号。开关将变换的信号提供给串行信号输出端子。开关由控制器控制，使得输入信号序列根据预定顺序被转换成串行信号序列。

6. 发明授权

US5917343A MOS inverter circuit 失效
标题翻译： MOS逆变电路
公开(公告)号：US5917343A
公开(公告)日：1999-06-29
申请号：US922680
申请日：1997-09-03
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H01L27/02 , H01L27/07 , H01L27/092 , H03K19/003 , H03K19/0948 , H01L27/00
CPC分类号： H01L27/0705 , H01L27/0203 , H01L27/0207 , H01L27/092 , H03K19/00384 , H01L2924/0002
摘要： A MOS inverter within a large scale integrated circuit (LSI) includes a pair of circuits with the same performance. Each of the circuits includes a plurality of MOS inverters serially connected from the first stage to the last stage. Each of the MOS inverters is provided with an input such that the input of the MOS inverters of the first stage are formed to be adjacent one another.
摘要翻译：大规模集成电路（LSI）中的MOS反相器包括具有相同性能的一对电路。每个电路包括从第一级到最后级串联连接的多个MOS反相器。每个MOS反相器具有输入，使得第一级的MOS反相器的输入形成为彼此相邻。

7. 发明授权

US5887024A Matched filter 失效
标题翻译：匹配过滤器
公开(公告)号：US5887024A
公开(公告)日：1999-03-23
申请号：US780145
申请日：1996-12-26
申请人： Xiaoling Qin , Kunihiko Suzuki , Guoliang Shou , Changming Zhou , Jie Chen
发明人： Xiaoling Qin , Kunihiko Suzuki , Guoliang Shou , Changming Zhou , Jie Chen
IPC分类号： H03H11/04 , H03H17/02 , H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： H03H11/04 , H03H17/02
摘要： The present invention provides a matched filter which can refresh an entire while keeping the speed of a calculation comparable to a small sized circuit. The first and second addition circuits of a matched filter of the present invention are classified into a plurality of groups, the first and second auxiliary adders replace functions for the groups of the first and second adders respectively. The outputs of the first and second adders are then inputted to the first and second subtractors, respectively, and the refreshing means appropriately refreshes the groups replaced by the first and second auxiliary adders. Further, the present invention decreases the number of auxiliary sapling and holding circuits to be used, and decides the refreshing intervals by considering the change of the voltage caused by leakage and other permissible errors of output voltage.
摘要翻译：本发明提供了一种匹配滤波器，其可以保持与小尺寸电路相当的计算速度的整体刷新。本发明的匹配滤波器的第一和第二加法电路分为多个组，第一和第二辅助加法器分别代替第一和第二加法器的组的功能。然后，第一和第二加法器的输出分别输入到第一和第二减法器，并且刷新装置适当地刷新由第一和第二辅助加法器替换的组。此外，本发明减少了要使用的辅助树苗和保持电路的数量，并且通过考虑由漏电引起的电压的变化和输出电压的其他允许误差来决定刷新间隔。

8. 发明授权

US5841315A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5841315A
公开(公告)日：1998-11-24
申请号：US686958
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Xiaoling Qin , Shengmin Lin , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Xiaoling Qin , Shengmin Lin , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03M1/66 , H03H11/04 , H03H17/02 , H03H19/00 , H03M3/02 , H03K5/00 , G11C27/02 , H03K12/00
CPC分类号： H04B1/7093 , H03H11/04 , H03H17/0254 , H04B1/7117
摘要： An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.
摘要翻译：本发明的目的是提供一种尺寸小且消耗低功率的匹配滤波电路。注意扩展码是1位数据串，输入信号被采样并保持为沿着时间序列的模拟信号，分为“1”和“-1”，分类信号通过电容耦合并联在根据本发明的匹配滤波器电路中。

9. 发明授权

US5740096A Filter circuit for communication 失效
公开(公告)号：US5740096A
公开(公告)日：1998-04-14
申请号：US708986
申请日：1996-09-06
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： H03M1/12 , H03H11/04 , H03H17/00 , H03H17/02 , H04B1/69 , H04J13/00 , G06G7/02
CPC分类号： H03H17/0254 , H03H11/04 , H04B1/7093
摘要： The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

10. 发明授权

US5661482A Interface circuit having a plurality of thresholding circuits 失效
标题翻译：接口电路具有多个阈值电路
公开(公告)号：US5661482A
公开(公告)日：1997-08-26
申请号：US536243
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03M1/34 , G06J1/00 , H03M1/74 , H03K19/0175 , H03K19/00
CPC分类号： G06J1/00
摘要： An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.
摘要翻译：一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，反相放大器电路，用于接收电容耦合的输出并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器，包括具有逐步阈值的多个阈值电路，模拟信号线被共同地输入到该阈值电路中，每个阈值电路通过加权接收具有较高阈值的阈值电路的输出，使得阈值电路将输出从高电平重复地改变为低电平或从低级到高级。

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