专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120144144A1 DYNAMIC MEMORY ALLOCATION AND RELOCATION TO CREATE LOW POWER REGIONS 有权
标题翻译：动态记忆分配与转型创造低功率地区
公开(公告)号：US20120144144A1
公开(公告)日：2012-06-07
申请号：US12961519
申请日：2010-12-07
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
IPC分类号： G06F12/02 , G06F11/30 , G06F12/00
CPC分类号： G06F3/0625 , G06F1/3275 , G06F3/0604 , G06F3/0631 , G06F3/0653 , G06F3/0673 , G06F12/0223 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.
摘要翻译：可以在计算机系统内分配和重新分配存储器对象，以将不经常使用的存储器对象合并到可以以较低功率运行的存储器区域。在记忆对象的初始分配期间，对象可以被放置在高功率区域中。在随后的周期性分析期间，不经常使用的高功率区域中的存储器对象可被重定位到较低功率区域，而经常使用的低功率区域中的存储器对象可能被移动到高功率区域。可以使用各种启发式或逻辑来处理不可移动的对象，共享对象和其他类型的对象。

2. 发明授权

US09235500B2 Dynamic memory allocation and relocation to create low power regions 有权
标题翻译：动态内存分配和重定位创建低功耗区域
公开(公告)号：US09235500B2
公开(公告)日：2016-01-12
申请号：US12961519
申请日：2010-12-07
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Swaroop Kavalanekar
IPC分类号： G06F11/30 , G06F12/00 , G06F12/02 , G06F1/32
CPC分类号： G06F3/0625 , G06F1/3275 , G06F3/0604 , G06F3/0631 , G06F3/0653 , G06F3/0673 , G06F12/0223 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.
摘要翻译：可以在计算机系统内分配和重新分配存储器对象，以将不经常使用的存储器对象合并到可以以较低功率运行的存储器区域。在记忆对象的初始分配期间，对象可以被放置在高功率区域中。在随后的周期性分析期间，不经常使用的高功率区域中的存储器对象可被重定位到较低功率区域，而经常使用的低功率区域中的存储器对象可能被移动到高功率区域。可以使用各种启发式或逻辑来处理不可移动的对象，共享对象和其他类型的对象。

3. 发明授权

US09015441B2 Memory usage scanning 有权
标题翻译：内存使用扫描
公开(公告)号：US09015441B2
公开(公告)日：2015-04-21
申请号：US12770937
申请日：2010-04-30
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F3/06 , G06F12/10 , G06F1/32 , G06F11/34
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3268 , G06F1/3275 , G06F3/0647 , G06F3/0688 , G06F11/3471 , G06F12/1009 , G06F2201/88 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/34
摘要： A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.
摘要翻译：存储器扫描系统可以通过使用存储在存储器中的处理的映射扫描每个存储器对象来扫描存储器对象来确定使用频率。可以多次执行扫描以产生每个页面或存储器单元的使用历史。在某些情况下，可以以不同的频率执行扫描以确定多种使用分类。该映射可以创建存储器使用的详细拓扑，包括访问频率的多个分类以及其他几个分类。基于拓扑，内存中的对象可能被复制到另一个存储介质中，或者针对性能或功耗进行了优化。

4. 发明申请

US20110271070A1 MEMORY USAGE SCANNING 有权
标题翻译：内存使用扫描
公开(公告)号：US20110271070A1
公开(公告)日：2011-11-03
申请号：US12770937
申请日：2010-04-30
申请人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
发明人： Bruce L. Worthington , Vishal Sharda , Qi Zhang , Mehmet Iyigun , Yevgeniy Bak
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0625 , G06F1/3225 , G06F1/3268 , G06F1/3275 , G06F3/0647 , G06F3/0688 , G06F11/3471 , G06F12/1009 , G06F2201/88 , Y02D10/13 , Y02D10/14 , Y02D10/154 , Y02D10/34
摘要： A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.
摘要翻译：存储器扫描系统可以通过使用存储在存储器中的处理的映射扫描每个存储器对象来扫描存储器对象来确定使用频率。可以多次执行扫描以产生每个页面或存储器单元的使用历史。在某些情况下，可以以不同的频率执行扫描以确定多种使用分类。该映射可以创建存储器使用的详细拓扑，包括访问频率的多个分类以及其他几个分类。基于拓扑，内存中的对象可能被复制到另一个存储介质中，或者针对性能或功耗进行了优化。

5. 发明申请

US20120284729A1 PROCESSOR STATE-BASED THREAD SCHEDULING 审中-公开
标题翻译：基于处理器状态的线程调度
公开(公告)号：US20120284729A1
公开(公告)日：2012-11-08
申请号：US13099660
申请日：2011-05-03
申请人： Vishal Sharda , Bruce L. Worthington
发明人： Vishal Sharda , Bruce L. Worthington
IPC分类号： G06F9/46
CPC分类号： G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： Techniques for implementing processor state-based thread scheduling are described that improve processor performance or energy efficiency of a computing device. In one or more embodiments, a power configuration state of a processor is ascertained. The processor or another processor is selected to execute a thread based on the power configuration state of the processor. In other embodiments, power configuration states of processor cores are ascertained. Power configuration state criteria for the processor cores are defined based on the respective power configuration states. One of the processor cores is then selected based on the power configuration state criteria to execute a thread.
摘要翻译：描述了用于实现基于处理器状态的线程调度的技术，其提高了计算设备的处理器性能或能量效率。在一个或多个实施例中，确定处理器的电源配置状态。选择处理器或另一个处理器以基于处理器的电源配置状态来执行线程。在其他实施例中，确定处理器核心的功率配置状态。基于相应的电源配置状态来定义处理器内核的电源配置状态标准。然后基于用于执行线程的功率配置状态标准来选择一个处理器核心。

6. 发明申请

US20130132616A1 CHARACTERIZING DEVICE PERFORMANCE BASED ON USER-PERCEIVABLE LATENCY 有权
标题翻译：基于用户可接受的延迟来表征设备性能
公开(公告)号：US20130132616A1
公开(公告)日：2013-05-23
申请号：US13299189
申请日：2011-11-17
申请人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
发明人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
IPC分类号： G06F3/00
CPC分类号： G06F11/3428 , G06F11/3419 , G06F11/3485 , G06F2201/81
摘要： A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.
摘要翻译：一种用于基于用户可感知延迟来表征设备的性能的方法和装置。为了表征设备性能，可以根据设备执行的操作的延迟来计算度量值。在计算度量的值时，可以不同地处理延迟，使得由设备的用户感知到的某些延迟可能对度量的值具有比不可感知的或被用户感知的其他潜伏期更大的影响在较小程度上。基于用户可感知延迟的这种性能度量促进了提供期望的用户体验的计算设备的识别。

7. 发明授权

US09223675B2 Characterizing device performance based on user-perceivable latency 有权
标题翻译：基于用户可感知的延迟来表征设备性能
公开(公告)号：US09223675B2
公开(公告)日：2015-12-29
申请号：US13299189
申请日：2011-11-17
申请人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
发明人： Bruce L. Worthington , Jason Carl Hendrickson , Robert P. Fitzgerald , Stuart Sechrest , Changjiu Xian , Qi Zhang
IPC分类号： G06F3/00 , G06F11/34 , G06F5/00
CPC分类号： G06F11/3428 , G06F11/3419 , G06F11/3485 , G06F2201/81
摘要： A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.
摘要翻译：一种用于基于用户可感知延迟来表征设备的性能的方法和装置。为了表征设备性能，可以根据设备执行的操作的延迟来计算度量值。在计算度量的值时，可以不同地处理延迟，使得由设备的用户感知到的某些延迟可能对度量的值具有比不可感知的或被用户感知的其他潜伏期更大的影响在较小程度上。基于用户可感知延迟的这种性能度量促进了提供期望的用户体验的计算设备的识别。

8. 发明授权

US07788435B2 Interrupt redirection with coalescing 有权
标题翻译：中断重定向与合并
公开(公告)号：US07788435B2
公开(公告)日：2010-08-31
申请号：US11971775
申请日：2008-01-09
申请人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
发明人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
IPC分类号： G06F13/24
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译：用于多处理器计算机的中断重定向和聚合系统。设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。

9. 发明申请

US20090177829A1 INTERRUPT REDIRECTION WITH COALESCING 有权
标题翻译：中断重定向与COALESCING
公开(公告)号：US20090177829A1
公开(公告)日：2009-07-09
申请号：US11971775
申请日：2008-01-09
申请人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
发明人： Bruce L. Worthington , Goran Marinkovic , Brian Railing , Qi Zhang , Swaroop V. Kavalanekar
IPC分类号： G06F13/24 , G06F9/44
CPC分类号： G06F9/4812
摘要： An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.
摘要翻译：用于多处理器计算机的中断重定向和聚合系统。设备使用通过PCI，PCI-X或PCI Express总线与存储器写入事务通信的预定义消息地址和数据有效负载中断处理器或处理器组。通过将多个中断通知组合成单个中断消息到处理器，可以提高处理效率。对于多处理器计算机上的一些中断，例如那些信令完成分配给设备的输入/输出（I / O）操作），处理器的处理效率可能随处理器而异。可以通过适当地聚合多个队列内和/或跨多个队列的中断消息来改善处理效率和整体计算机系统操作，其中中断基于他们所针对的哪个处理器进行排队。

10. 发明授权

US08479214B2 Hardware throughput saturation detection 有权
标题翻译：硬件吞吐量饱和度检测
公开(公告)号：US08479214B2
公开(公告)日：2013-07-02
申请号：US12242621
申请日：2008-09-30
申请人： Dustin L. Green , Yau Ning Chin , Bruce L. Worthington
发明人： Dustin L. Green , Yau Ning Chin , Bruce L. Worthington
IPC分类号： G06F13/00
CPC分类号： G06F9/4881
摘要： Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.
摘要翻译：当硬件设备饱和IO作业时，可以实现改进的硬件吞吐量。吞吐量可以基于输入IO作业的可量化特征来估计。当接收到IO作业时，可以估计每个作业的时间成本并将其存储在内存中。估计值可用于计算飞行中IO作业的总时间成本，并可根据IO作业的完成时间确定硬件设备是否饱和。随着时间的推移，IO作业的时间成本估算可以根据IO作业的估计时间成本与使用汇总IO作业完成序列的IO作业的实际时间成本进行比较来修改。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式