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1. 发明授权

US09515086B2 Semiconductor device, electronic device, and method of fabricating the same 有权
标题翻译：半导体器件，电子器件及其制造方法
公开(公告)号：US09515086B2
公开(公告)日：2016-12-06
申请号：US14834454
申请日：2015-08-25
申请人： Gukhyon Yon , Jaeyoung Ahn , Bio Kim , Young-Jin Noh , Kwangmin Park , Dongchul Yoo
发明人： Gukhyon Yon , Jaeyoung Ahn , Bio Kim , Young-Jin Noh , Kwangmin Park , Dongchul Yoo
IPC分类号： H01L27/115 , H01L29/51 , H01L21/02 , H01L21/28 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/28273 , H01L21/28282 , H01L27/11556 , H01L29/511 , H01L29/517 , H01L29/518 , H01L29/7926
摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.
摘要翻译：提供三维半导体存储器件及其制造方法。在三维半导体存储器件中，可以在衬底上形成一叠栅极电极和绝缘层，沟道结构可以延伸通过堆叠并连接至衬底。可以在每个栅电极和沟道结构之间形成阻挡绝缘层，电荷存储层和隧道绝缘层。隧道绝缘层可以包括具有低电荷陷阱位点密度的高k电介质层。隧道绝缘层还可以包括第一和第二隧道绝缘层，并且高k电介质层设置在第一和第二隧道绝缘层之间。

2. 发明授权

US09490371B2 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09490371B2
公开(公告)日：2016-11-08
申请号：US14539043
申请日：2014-11-12
申请人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
发明人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
IPC分类号： H01L29/792 , H01L29/66 , H01L27/115
CPC分类号： H01L29/7926 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
摘要翻译：非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

3. 发明申请

US20150194440A1 Nonvolatile Memory Devices And Methods Of Fabricating The Same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20150194440A1
公开(公告)日：2015-07-09
申请号：US14539043
申请日：2014-11-12
申请人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
发明人： Young-Jin Noh , Bio Kim , Kwangmin Park , Jaeyoung Ahn , SeungHyun Lim , JaeHo Choi , Jumi Yun , Ji-Hoon Choi
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/7926 , H01L27/1157 , H01L27/11582 , H01L29/66833 , H01L29/792
摘要： A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
摘要翻译：非易失性存储器件包括栅极结构，栅极结构包括垂直堆叠在衬底上的栅极间绝缘图案和介于栅间绝缘图案之间的栅极电极，通过栅极结构连接到衬底的垂直有源柱，电荷存储垂直有源柱和栅电极之间的层，电荷存储层和垂直有源柱之间的隧道绝缘层，以及电荷存储层和栅电极之间的阻挡绝缘层。电荷存储层包括分别与隔离绝缘层和隧道绝缘层相邻的第一和第二电荷存储层。第一电荷存储层包括氮化硅层，第二电荷存储层包括氮氧化硅层。

4. 发明申请

US20070167030A1 Method of forming an insulation structure and method of manufacturing a semiconductor device using the same 有权
标题翻译：绝缘结构的形成方法及其制造方法
公开(公告)号：US20070167030A1
公开(公告)日：2007-07-19
申请号：US11639164
申请日：2006-12-15
申请人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
发明人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/3144 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L27/115 , H01L27/11521
摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
摘要翻译：在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

5. 发明申请

US20090134450A1 Tunneling insulating layer, flash memory device including the same, memory card and system including the flash memory device, and methods of manufacturing the same 审中-公开
标题翻译：隧道绝缘层，包括其的闪存装置，包括闪存装置的存储卡和系统及其制造方法
公开(公告)号：US20090134450A1
公开(公告)日：2009-05-28
申请号：US12153686
申请日：2008-05-22
申请人： Chul-sung Kim , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Young-Jin Noh
发明人： Chul-sung Kim , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Young-Jin Noh
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , G11C16/0416 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/513 , H01L29/7881
摘要： Provided is a tunneling insulating layer, a flash memory device including the same that increases a program/erase operation speed of the flash memory device and has improved data retention in order to increase reliability of the flash memory device, a memory card and system including the flash memory device, and methods of manufacturing the same. A tunneling insulating layer may include a first region and a second region on the first region, wherein the first region has a first nitrogen atomic percent, the second region has a second nitrogen atomic percent, and the second nitrogen atomic percent is less than the first nitrogen atomic percent. The flash memory device according to example embodiments may include a substrate including source and drain regions and a channel region between the source and drain regions, the tunneling insulating layer on the channel region, a charge storage layer on the tunneling insulating layer, a blocking insulation layer on the charge storage layer, and a gate electrode on the blocking insulation layer.
摘要翻译：提供了一种隧道绝缘层，包括其的闪速存储器件，其提高闪速存储器件的编程/擦除操作速度，并且具有改进的数据保持以便提高闪存器件的可靠性，存储卡和系统包括闪存装置及其制造方法。隧道绝缘层可以包括在第一区域上的第一区域和第二区域，其中第一区域具有第一氮原子百分比，第二区域具有第二氮原子百分比，第二氮原子百分比小于第一区域的第一区域氮原子百分比。根据示例性实施例的闪速存储器件可以包括：衬底，其包括源极和漏极区域以及在源极和漏极区域之间的沟道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的电荷存储层，阻挡绝缘层电荷存储层上的栅极电极和阻挡绝缘层上的栅电极。

6. 发明授权

US09698233B2 Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same 有权
公开(公告)号：US09698233B2
公开(公告)日：2017-07-04
申请号：US14644408
申请日：2015-03-11
申请人： Eun-Yeoung Choi , Young-Jin Noh , Bi-O Kim , Kwang-Min Park , Jae-Young Ahn , Ju-Mi Yun , Jae-Ho Choi , Ki-Hyun Hwang
发明人： Eun-Yeoung Choi , Young-Jin Noh , Bi-O Kim , Kwang-Min Park , Jae-Young Ahn , Ju-Mi Yun , Jae-Ho Choi , Ki-Hyun Hwang
IPC分类号： H01L29/792 , H01L29/51 , H01L27/11582 , H01L21/28
CPC分类号： H01L29/513 , H01L21/28282 , H01L27/11582 , H01L29/518
摘要： Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

7. 发明申请

US20110275190A1 METHOD OF FORMING AN INSULATION STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成绝缘结构的方法及使用其制造半导体器件的方法
公开(公告)号：US20110275190A1
公开(公告)日：2011-11-10
申请号：US13188587
申请日：2011-07-22
申请人： Jung-Geun JEE , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
发明人： Jung-Geun JEE , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/3144 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L27/115 , H01L27/11521
摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
摘要翻译：在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

8. 发明授权

US07608509B2 Method of manufacturing a flash memory device having compensation members formed on edge portions of a tunnel oxide layer 有权
标题翻译：制造具有形成在隧道氧化物层的边缘部分上的补偿部件的闪存装置的方法
公开(公告)号：US07608509B2
公开(公告)日：2009-10-27
申请号：US11494439
申请日：2006-07-27
申请人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Sung-Kweon Baek , Young-Jin Noh
发明人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Sung-Kweon Baek , Young-Jin Noh
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.
摘要翻译：在半导体器件和半导体器件的制造方法中，在衬底上形成具有突出的上部的预备隔离区以限定有源区。在有源区上形成绝缘层之后，在绝缘层上形成第一导电层。去除预分离区域的突出的上部，以在衬底上形成隔离区域并暴露第一导电层的侧壁，并且补偿构件形成在绝缘层的边缘部分上。补偿构件可以补充绝缘层的边缘部分，该边缘部分的厚度基本上比绝缘层的中心部分的厚度更薄，并且可以防止绝缘层的劣化。此外，具有基本上大于有源区的宽度的第一导电层可以增强半导体器件的耦合比。因此，半导体器件可以具有改善的电特性和可靠性。

9. 发明申请

US20080090354A1 Method of Manufacturing a Non-Volatile Memory Device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080090354A1
公开(公告)日：2008-04-17
申请号：US11868195
申请日：2007-10-05
申请人： Sung-Kweon Baek , Bon-Young Koo , Chul-Sung Kim , Jung-Geun Jee , Young-Jin Noh
发明人： Sung-Kweon Baek , Bon-Young Koo , Chul-Sung Kim , Jung-Geun Jee , Young-Jin Noh
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.
摘要翻译：一种制造非易失性存储器件的方法包括通过同时氧化和氮化处理在衬底上形成包含氧氮化物的隧道隔离层，其中使用包括氧和氮的处理气体同时进行氧化过程和氮化处理。该方法还包括进行第一和第二热处理以分别在包括氮（N）和氯（Cl）的气体环境中从隧道隔离层去除缺陷位点，并在第二热处理之后在隧道隔离层上形成栅结构，以及在与栅极结构相邻的衬底的表面部分处形成源极/漏极区域。

10. 发明申请

US20070026655A1 Method of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070026655A1
公开(公告)日：2007-02-01
申请号：US11489985
申请日：2006-07-20
申请人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Ji-Hyun Kim , Young-Jin Noh
发明人： Chul-Sung Kim , Yu-Gyun Shin , Bon-Young Koo , Ji-Hyun Kim , Young-Jin Noh
IPC分类号： H01L21/473
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a method of manufacturing a semiconductor device for use in such applications as a flash memory device, a field insulating pattern defines an opening that exposes an active region of a semiconductor substrate. The field insulating pattern includes a first portion protruding from the substrate and a second portion buried in the substrate. An oxide layer is formed on the active region by an oxidation process using a reactive plasma including an oxygen radical and a conductive layer is then formed on the oxide layer to sufficiently fill up the opening. The oxide layer is formed by an oxidation reaction of a surface portion of the active region with the oxygen radical having a relatively low activation energy, resulting in an improved thickness uniformity of the oxide layer. As a result, various performance characteristics of the semiconductor device when used in flash memory and similar applications are improved.
摘要翻译：在制造用于诸如闪速存储器件的应用中的半导体器件的方法中，场绝缘图案限定了露出半导体衬底的有源区的开口。场绝缘图案包括从基板突出的第一部分和埋在基板中的第二部分。通过使用包含氧自由基的反应性等离子体的氧化工艺在有源区上形成氧化物层，然后在氧化物层上形成导电层以充分填充开口。通过活性区域的表面部分与具有相对较低的活化能的氧自由基的氧化反应形成氧化物层，从而改善氧化物层的厚度均匀性。结果，改善了当用于闪速存储器和类似应用时半导体器件的各种性能特性。

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