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1. 发明授权

US09997530B2 Three-dimensional semiconductor memory device and method of fabricating the same 有权
公开(公告)号：US09997530B2
公开(公告)日：2018-06-12
申请号：US14708477
申请日：2015-05-11
申请人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
发明人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/24 , H01L27/11578 , H01L27/11556 , H01L27/11575 , H01L45/00
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

2. 发明申请

US20170287929A1 SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170287929A1
公开(公告)日：2017-10-05
申请号：US15514239
申请日：2014-09-26
申请人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
发明人： Sunggil KIM , Phil Ouk NAM , Gukhyon YON , Sunghae LEE , Woojin JANG , Dongchul YOO , Hunhyeong LIM , Junggeun JEE , Kihyun HWANG
IPC分类号： H01L27/11582 , H01L21/02 , H01L21/28 , H01L21/311 , H01L27/1157 , H01L29/10
CPC分类号： H01L27/11582 , H01L21/0206 , H01L21/31116 , H01L27/115 , H01L27/1157 , H01L28/00 , H01L29/1037 , H01L29/40117
摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

3. 发明申请

US20140070302A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20140070302A1
公开(公告)日：2014-03-13
申请号：US13974122
申请日：2013-08-23
申请人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
发明人： Dongchul YOO , Phil Ouk NAM , Junkyu YANG , Woong LEE , Woosung LEE , JinGyun KIM , Daehong EOM
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/04 , H01L29/1037 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/511 , H01L29/7926
摘要： A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
摘要翻译：一种三维（3D）半导体存储器件及其制造方法，该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构，分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构，垂直结构分别包括半导体柱; 和外延图案，每个外延图案在衬底和每个垂直结构之间，其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

4. 发明申请

US20110233648A1 Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20110233648A1
公开(公告)日：2011-09-29
申请号：US13072078
申请日：2011-03-25
申请人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
发明人： Kwang Soo Seol , Chanjin Park , Kihyun Hwang , Hanmei Choi , Dongchul Yoo , Sunghoi Hur , Wansik Hwang , Toshiro Nakanishi , Kwangmin Park , Juyul Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/42348 , H01L21/32137 , H01L27/0688 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/511 , H01L29/517 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
摘要翻译：三维半导体存储器件及其制造方法。三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

5. 发明授权

US09960046B2 Methods of manufacturing semiconductor device having a blocking insulation layer 有权
公开(公告)号：US09960046B2
公开(公告)日：2018-05-01
申请号：US15609099
申请日：2017-05-31
申请人： Jung Ho Kim , Bio Kim , Jaeyoung Ahn , Dongchul Yoo
发明人： Jung Ho Kim , Bio Kim , Jaeyoung Ahn , Dongchul Yoo
IPC分类号： H01L21/28 , H01L27/1157 , H01L27/11582 , H01L21/02
CPC分类号： H01L21/28282 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of each other a substrate, forming a vertical hole that penetrates the insulation layers and the sacrificial layers, and forming a vertical channel structure in the vertical hole. The forming the vertical channel structure includes forming a blocking insulation layer, a charge storage layer, a tunnel insulation layer, and a semiconductor pattern. The forming the blocking insulation layer includes forming a first oxidation target layer, oxidizing the first oxidation target layer to form a first sub-blocking layer, and forming a second sub-blocking layer. The first sub-blocking layer is formed between the second sub-blocking layer and an inner sidewall of the vertical hole.

6. 发明授权

US09397114B2 Methods of fabricating three-dimensional semiconductor memory devices 有权
标题翻译：制造三维半导体存储器件的方法
公开(公告)号：US09397114B2
公开(公告)日：2016-07-19
申请号：US13475023
申请日：2012-05-18
申请人： Jumi Yun , Kwangmin Park , Dongchul Yoo , Byong-hyun Jang
发明人： Jumi Yun , Kwangmin Park , Dongchul Yoo , Byong-hyun Jang
IPC分类号： H01L27/00 , H01L21/00 , H01L27/115 , H01L21/31 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/31 , H01L29/7926
摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.
摘要翻译：制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

7. 发明申请

US20160049423A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160049423A1
公开(公告)日：2016-02-18
申请号：US14695249
申请日：2015-04-24
申请人： Dongchul YOO , Chaeho KIM , Jaeyoung AHN , Woong LEE
发明人： Dongchul YOO , Chaeho KIM , Jaeyoung AHN , Woong LEE
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.
摘要翻译：三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案通道孔，但不在虚拟孔中。

8. 发明申请

US20150372005A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20150372005A1
公开(公告)日：2015-12-24
申请号：US14708477
申请日：2015-05-11
申请人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
发明人： Gukhyon Yon , Dongwoo Kim , Kihyun Hwang , Dongkyum Kim , Dongchul Yoo
IPC分类号： H01L27/115 , H01L45/00 , H01L23/528 , H01L27/24
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.
摘要翻译：一种三维半导体存储器件，包括在基板上的外围电路结构，外围电路结构上的水平有源层，设置在水平有源层上的堆叠，包括多个电极，垂直穿过堆叠的垂直结构，源区域，以及水平有源层中的拾取区域。水平有源层包括顺序堆叠在外围电路结构上的第一，第二和第三有源半导体层。掺杂第一和第三有源半导体层分别具有高和低杂质浓度，第二有源半导体层包括杂质扩散抑制材料。

9. 发明授权

US09175812B2 Lighting apparatus 有权
标题翻译：照明设备
公开(公告)号：US09175812B2
公开(公告)日：2015-11-03
申请号：US13312012
申请日：2011-12-06
申请人： Byungsang Jung , Sejoon You , Kyungtaek Lee , Hyunha Kim , Seoyoung Maeng , Dongchul Yoo
发明人： Byungsang Jung , Sejoon You , Kyungtaek Lee , Hyunha Kim , Seoyoung Maeng , Dongchul Yoo
IPC分类号： F21V29/507 , F21K99/00 , F21V29/63 , F21V29/77 , F21Y101/02 , F21Y103/02
CPC分类号： F21K9/13 , F21K9/23 , F21V29/507 , F21V29/63 , F21V29/773 , F21Y2103/33 , F21Y2115/10 , H01L2224/48091 , H01L2224/48464 , H01L2224/73265 , H01L2924/00014
摘要： A lighting apparatus can dissipate heat by conduction and convection. A heat sink is provided with an active cooling device for the lighting apparatus.
摘要翻译：照明装置可以通过传导和对流散热。散热器设置有用于照明装置的主动冷却装置。

10. 发明申请

US20150279857A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279857A1
公开(公告)日：2015-10-01
申请号：US14539140
申请日：2014-11-12
申请人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
发明人： Jung-Hwan KIM , Hanvit YANG , Jintae NOH , Dongchul YOO
IPC分类号： H01L27/115 , H01L23/00
CPC分类号： H01L27/11582
摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.
摘要翻译：本发明的概念提供半导体存储器件及其制造方法。堆叠结构和垂直通道结构设置在基板上。堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。第一垂直通道图案设置在每个垂直通道结构的下部。栅极氧化层形成在第一垂直沟道图案的侧壁上。在垂直通道结构之间的衬底中形成凹陷区域。在凹陷区域中形成缓冲氧化物层。在基板中设置氧化抑制层以包围凹部。氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。

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