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1. 发明授权

US06645862B2 Double-side polishing process with reduced scratch rate and device for carrying out the process 有权
标题翻译：减少划伤率的双面抛光工艺和进行该工艺的装置
公开(公告)号：US06645862B2
公开(公告)日：2003-11-11
申请号：US09989550
申请日：2001-11-20
申请人： Guido Wenski , Johann Glas , Thomas Altmann , Gerhard Heier
发明人： Guido Wenski , Johann Glas , Thomas Altmann , Gerhard Heier
IPC分类号： H01L21302
CPC分类号： H01L21/02024 , B24B37/0056 , B24B37/08
摘要： A process for producing semiconductor wafers by double-sided polishing between two rotating, upper and lower polishing plates, which are covered with polishing cloth, while an alkaline polishing abrasive with colloidal solid fractions is being supplied, the semiconductor wafers being guided by carriers which have circumferential gear teeth and are set in rotation by complementary outer gear teeth and inner gear teeth of the polishing machine, which is distinguished by the following process steps: (a) at least one of the two sets of gear teeth of the polishing machine is at least from time to time sprayed with a liquid which substantially comprises water, (b) the alkaline polishing abrasive is fed continuously to the semiconductor wafers in a closed supply device. There is also a device which is suitable for carrying out the process.
摘要翻译：在提供具有胶体固体部分的碱性抛光磨料的同时，在被抛光布覆盖的两个旋转，上和下抛光板之间通过双面抛光来生产半导体晶片的方法，半导体晶片由具有周向齿轮齿，并由抛光机的互补外齿轮齿和内齿轮齿旋转，其特征在于以下工艺步骤：（a）抛光机的两组齿轮齿中的至少一个处于至少不时地用基本上包含水的液体喷雾，（b）碱性抛光磨料在封闭的供应装置中连续地供给到半导体晶片。还有一种适用于执行该过程的装置。

2. 发明授权

US06899762B2 Epitaxially coated semiconductor wafer and process for producing it 失效
标题翻译：外延涂层半导体晶片及其制造方法
公开(公告)号：US06899762B2
公开(公告)日：2005-05-31
申请号：US10402171
申请日：2003-03-28
申请人： Guido Wenski , Wolfgang Siebert , Klaus Messmann , Gerhard Heier , Thomas Altmann , Martin Fürfanger
发明人： Guido Wenski , Wolfgang Siebert , Klaus Messmann , Gerhard Heier , Thomas Altmann , Martin Fürfanger
IPC分类号： C30B29/06 , B24B37/04 , H01L21/02 , H01L21/205 , H01L21/304 , H01L21/306 , C30B25/14
CPC分类号： B24B37/08 , B24B37/042 , H01L21/02024 , H01L21/30625 , Y10T428/24355
摘要： A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmax of less than or equal to 0.13 μm and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 μm×1 μm reference area. Furthermore, there is a process for producing the semiconductor wafer. The process includes the following process steps: (a) as a single polishing step, simultaneous polishing of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while an alkaline polishing slurry is being supplied, the semiconductor wafer lying in a cutout of a carrier whose thickness is dimensioned to be 2 to 20 μm less than the thickness of the semiconductor wafer after the latter has been polished; (b) simultaneous treatment of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while a liquid containing at least one polyhydric alcohol having 2 to 6 carbon atoms is being supplied; (c) cleaning and drying of the semiconductor wafer; and (d) deposition of the epitaxial layer on the front surface of the semiconductor wafer produced in accordance with steps (a) to (c).
摘要翻译：具有前表面和后表面的半导体晶片和沉积在前表面上的半导体材料的外延层。在半导体晶片中，外延层具有小于或等于0.13μm的最大局部平坦度值SFQR＆lt; SUB＆lt;＆lt; SUB＆lt; SUB＆gt;和最大密度为0.14散射光中心/ cm 2 。在沉积外延层之前，半导体晶片的前表面在1mum×1mum参考区域上通过AFM测量的表面粗糙度为0.05至0.29nm RMS。此外，存在制造半导体晶片的工艺。该方法包括以下工艺步骤：（a）作为单个抛光步骤，在供应碱性抛光浆料的同时，在旋转的抛光板之间同时抛光半导体晶片的表面和背面，半导体晶片位于载体的切口，其尺寸设定为比后半导体晶片抛光后的半导体晶片的厚度小2〜20μm; （b）在供给包含至少一种含有2〜6个碳原子的多元醇的液体的同时处理旋转研磨板之间的半导体晶片的前表面和后表面; （c）清洗和干燥半导体晶片; 以及（d）在根据步骤（a）至（c）制造的半导体晶片的前表面上沉积外延层。

3. 发明授权

US06793837B2 Process for material-removing machining of both sides of semiconductor wafers 有权
标题翻译：用于半导体晶片两侧材料去除加工的工艺
公开(公告)号：US06793837B2
公开(公告)日：2004-09-21
申请号：US10174139
申请日：2002-06-18
申请人： Guido Wenski , Thomas Altmann , Gerhard Heier , Wolfgang Winkler , Gunther Kann
发明人： Guido Wenski , Thomas Altmann , Gerhard Heier , Wolfgang Winkler , Gunther Kann
IPC分类号： B44C122
CPC分类号： H01L21/02024 , B24B17/10 , B24B37/08
摘要： A process is for material-removing machining, on both sides simultaneously, of semiconductor wafers having a front surface and a back surface, the semiconductor wafers resting in carriers which are set in rotation by means of an annular outer drive ring and an annular inner drive ring and being moved between two oppositely rotating working disks in a manner which can be described by means of in each case one path curve relative to the upper working disk and one path curve relative to the lower working disk, wherein the two path curves after six loops around the center have the appearance of still being open, and at each point have a radius of curvature which is at least as great as the radius of the inner drive ring.
摘要翻译：一种方法是在半导体晶片具有前表面和后表面的同时在两面同时进行材料去除加工，半导体晶片位于载体中，该载体通过环形外驱动环和环形内驱动在两个相对旋转的工作盘之间移动，可以通过在每种情况下通过相对于上工作盘的一个路径曲线和相对于下工作盘的一个路径曲线来描述，其中在六个之后的两个路径曲线围绕中心的环路具有仍然是开放的外观，并且在每个点处具有至少与内部驱动环的半径一样大的曲率半径。

4. 发明授权

US06583050B2 Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer 有权
公开(公告)号：US06583050B2
公开(公告)日：2003-06-24
申请号：US10218006
申请日：2002-08-13
申请人： Guido Wenski , Thomas Altmann , Ernst Feuchtinger , Willibald Bernwinkler , Wolfgang Winkler , Gerhard Heier
发明人： Guido Wenski , Thomas Altmann , Ernst Feuchtinger , Willibald Bernwinkler , Wolfgang Winkler , Gerhard Heier
IPC分类号： H01L214763
CPC分类号： H01L21/02024 , B24B37/042 , B24B37/08
摘要： A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.

5. 发明授权

US06514424B2 Process for the double-side polishing of semiconductor wafers and carrier for carrying out the process 有权
标题翻译：用于半导体晶片和载体的双面抛光的工艺用于实施该工艺
公开(公告)号：US06514424B2
公开(公告)日：2003-02-04
申请号：US09826135
申请日：2001-04-04
申请人： Guido Wenski , Gerhard Heier , Wolfgang Winkler , Thomas Altmann
发明人： Guido Wenski , Gerhard Heier , Wolfgang Winkler , Thomas Altmann
IPC分类号： H01L2100
CPC分类号： B24B41/067 , B24B37/08 , H01L21/02024
摘要： A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.
摘要翻译：在两个抛光板之间进行双面抛光的方法，该两个抛光板以相反的方向旋转并被抛光布覆盖，以至于除去了至少2微米的半导体材料。半导体晶片放置在由钢制成的多组平面载体的一组塑料衬里的切口中，其平均厚度比完全抛光的半导体晶片的平均厚度小2至20μm。该集合仅包括厚度差为5mum以下的载波，属于该集合的每个载波具有至少一个明确的识别特征，将其分配给该集合。使用包含在识别特征中的信息项目，以便以固定的间隔更换塑料衬里，并确保半导体晶片在抛光之后保持与抛光之前相同的顺序。还有一个适用于执行该过程的载体。

6. 发明授权

US06458688B1 Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer 有权
标题翻译：具有改善的平坦度的半导体晶片，以及用于制造半导体晶片的工艺
公开(公告)号：US06458688B1
公开(公告)日：2002-10-01
申请号：US09491649
申请日：2000-01-27
申请人： Guido Wenski , Thomas Altmann , Ernst Feuchtinger , Willibald Bernwinkler , Wolfgang Winkler , Gerhard Heier
发明人： Guido Wenski , Thomas Altmann , Ernst Feuchtinger , Willibald Bernwinkler , Wolfgang Winkler , Gerhard Heier
IPC分类号： H01L214763
CPC分类号： H01L21/02024 , B24B37/042 , B24B37/08
摘要： A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQRmax of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.
摘要翻译：半导体晶片具有基于半导体晶片的前表面上的表面格栅的部分区域的前表面和后表面以及平坦度值，其具有小于或等于0.13μm的最大局部平坦度值SFQRmax和单独的SFQR 在半导体晶片的周边区域中的值与半导体晶片的中心区域的值没有显着差异。还有一种制造该半导体晶片的方法，其中半导体晶片的起始厚度比载体的厚度大20至200微米，并且半导体晶片被抛光直到半导体晶片的端部厚度为2至20μm 大于载体的厚度。

7. 发明授权

US07541287B2 Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method 有权
标题翻译：在通过该方法制造的载体，载体和半导体晶片的两侧加工半导体晶片的方法
公开(公告)号：US07541287B2
公开(公告)日：2009-06-02
申请号：US11487652
申请日：2006-07-17
申请人： Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
发明人： Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
IPC分类号： H01L21/302
CPC分类号： B24B37/28 , Y10S438/959
摘要： A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
摘要翻译：半导体晶片被引导在载体的切口中，同时通过从前表面和背面去除材料将半导体晶片的厚度减小到目标厚度。半导体晶片被加工直到其比载体体薄并且比用于将载体上的切口对准的嵌体更厚以保护半导体晶片。载体的特征在于，在半导体晶片的加工整个整个持续时间内，载体主体和嵌体具有不同的厚度，载体主体比镶嵌物厚20〜70μm。该方法提供在两侧抛光的半导体晶片，具有前表面，后表面和边缘以及前表面的局部平坦度，SFQRmax小于50nm，边缘排除R-2mm和小于nm，基于26×8mm的场地面积，R-1mm的边缘排除。

8. 发明申请

US20070021042A1 Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method 有权
标题翻译：在通过该方法制造的载体，载体和半导体晶片的两侧加工半导体晶片的方法
公开(公告)号：US20070021042A1
公开(公告)日：2007-01-25
申请号：US11487652
申请日：2006-07-17
申请人： Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
发明人： Ruediger Schmolke , Thomas Buschhardt , Gerhard Heier , Guido Wenski
IPC分类号： B24B7/00
CPC分类号： B24B37/28 , Y10S438/959
摘要： A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. The method provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than 115 nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
摘要翻译：半导体晶片被引导在载体的切口中，同时通过从前表面和背面去除材料将半导体晶片的厚度减小到目标厚度。半导体晶片被加工直到其比载体体薄并且比用于将载体上的切口对准的嵌体更厚以保护半导体晶片。载体的特征在于，在半导体晶片的加工整个整个持续时间内，载体主体和嵌体具有不同的厚度，载体主体比镶嵌物厚20〜70μm。该方法提供在两侧抛光的半导体晶片，具有前表面，后表面和边缘以及前表面的局部平坦度，SFQR 小于50nm，边缘排除 R-2mm和小于115nm，边缘排除R-1mm，基于26×8mm的位置面积。

9. 发明授权

US06861360B2 Double-sided polishing process for producing a multiplicity of silicon semiconductor wafers 有权
标题翻译：用于制造多个硅半导体晶片的双面抛光工艺
公开(公告)号：US06861360B2
公开(公告)日：2005-03-01
申请号：US10294846
申请日：2002-11-14
申请人： Guido Wenski , Thomas Altmann , Anton Huber , Alexander Heilmaier
发明人： Guido Wenski , Thomas Altmann , Anton Huber , Alexander Heilmaier
IPC分类号： B24B37/04 , B24B49/16 , C30B29/06 , C30B33/00 , H01L21/302 , H01L21/304 , H01L21/306
CPC分类号： H01L21/02024 , B24B37/0056 , B24B37/042 , B24B37/08 , B24B49/16
摘要： A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQRmax of less than or equal to 0.13 μm, based on a surface grid of segments with a size of 26 mm×8 mm on the front surface, wherein the maximum local height deviation P/V(10×10)max of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×10 mm. There is also a process for producing a multiplicity of silicon semiconductor wafers by simultaneous double-side polishing between in each case one lower polishing plate and one upper polishing plate, which rotate, are parallel to one another and to which polishing cloth has been adhesively bonded, while a polishing agent, which contains abrasives or colloids, is being supplied, with at least 2 μm of silicon being removed, wherein a predetermined proportion of the semiconductor wafers is at least partially polished using a lower polishing pressure, and a further proportion of the semiconductor wafers is polished using a higher polishing pressure.
摘要翻译：具有大于或等于200mm的直径的硅半导体晶片和抛光的前表面和抛光后表面以及小于或等于0.13μm的最大局部平坦度值SFQRmax，基于具有尺寸为26mm×8mm的前表面，其中，从理想平面的前表面的最大局部高度偏差P / V（10×10）max小于或等于70nm，基于尺寸为10mm×10mm的滑动子区域。还有一种通过在每种情况下同时进行双面抛光来生产多个硅半导体晶片的方法，其中一个下抛光板和一个上抛光板相互平行，并且抛光布已经被粘合到该抛光板上同时提供含有研磨剂或胶体的抛光剂，除去至少2个微米的硅，其中使用较低的抛光压力至少部分地抛光半导体晶片的预定比例，另外一部分使用更高的抛光压力来抛光半导体晶片。

10. 发明授权

US5072069A Cycloolefinic complexes of platinum, processes for preparing the same and their use as a catalyst 失效
标题翻译：铂的环状络合物，其制备方法及其作为催化剂的用途
公开(公告)号：US5072069A
公开(公告)日：1991-12-10
申请号：US485704
申请日：1990-02-27
申请人： Guido Wenski , Ludwig Maier , Hans-Jurgen Eberle
发明人： Guido Wenski , Ludwig Maier , Hans-Jurgen Eberle
IPC分类号： B01J31/22 , C07B61/00 , C07C5/03 , C07C5/22 , C07C13/02 , C07C45/50 , C07F7/08 , C07F15/00
CPC分类号： C07F15/0093 , B01J31/2295 , C07F15/0086 , B01J2231/14 , B01J2231/321 , B01J2231/323 , B01J2231/52 , B01J2231/64 , B01J2531/828
摘要： The invention relates to cycloolefinic complexes of platinum, processes for preparing the same from platinum(II) compounds and cyclolefins having at least 12 ring carbon atoms and at least two aliphatic non-cumulated carbon-carbon double bonds and their use as a catalyst for the addition of Si-bonded hydrogen to an aliphatic multiple bond.
摘要翻译：本发明涉及铂的环烯烃络合物，其由铂（II）化合物制备的方法及具有至少12个环碳原子的环烯烃和至少两个脂肪族非累积碳 - 碳双键，以及它们作为催化剂的用途将Si键合的氢加成脂肪族多键。

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