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1. 发明授权

US07368394B2 Etch methods to form anisotropic features for high aspect ratio applications 失效
标题翻译：蚀刻方法来形成高纵横比应用的各向异性特征
公开(公告)号：US07368394B2
公开(公告)日：2008-05-06
申请号：US11363834
申请日：2006-02-27
申请人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
发明人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/32137 , H01L21/76814
摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要翻译：在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面层。

2. 发明申请

US20070202700A1 Etch methods to form anisotropic features for high aspect ratio applications 审中-公开
标题翻译：蚀刻方法来形成高纵横比应用的各向异性特征
公开(公告)号：US20070202700A1
公开(公告)日：2007-08-30
申请号：US11363789
申请日：2006-02-27
申请人： Uwe Leucke , Meihua Shen , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
发明人： Uwe Leucke , Meihua Shen , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： C23F4/00 , H01L21/3065 , H01L21/3086 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要翻译：在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面层。

3. 发明申请

US20070199922A1 Etch methods to form anisotropic features for high aspect ratio applications 失效
公开(公告)号：US20070199922A1
公开(公告)日：2007-08-30
申请号：US11363834
申请日：2006-02-27
申请人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
发明人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
IPC分类号： H01L21/461 , B44C1/22 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/32137 , H01L21/76814
摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

4. 发明申请

US20060252265A1 Etching high-kappa dielectric materials with good high-kappa foot control and silicon recess control 审中-公开
标题翻译：蚀刻具有良好的高kappa脚控制和硅凹槽控制的高kappa介电材料
公开(公告)号：US20060252265A1
公开(公告)日：2006-11-09
申请号：US11126472
申请日：2005-05-11
申请人： Guangxiang Jin , Meihua Shen
发明人： Guangxiang Jin , Meihua Shen
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/31122 , H01L21/31637 , H01L21/31641 , H01L21/31645
摘要： An apparatus and a method for etching high dielectric constant (high-κ) materials using halogen containing gas and reducing gas chemistries are provided. One embodiment of the method is accomplished by etching a layer using two etch gas chemistries in separate steps. The first etch gas chemistry contain no oxygen containing gas in order to break through etching of the high dielectric constant materials, to dean any residues left from previous polysilicon etch process resulting in less high-κ foot, and also to control silicon recess problem associated with an underlying silicon oxide layer. The second over-etch gas chemistry provides a high etch selectivity for high dielectric constant materials over silicon oxide materials to be combined with low source power to further reduce silicon substrate oxidation problem.
摘要翻译：提供了使用含卤素气体和还原气体化学物质蚀刻高介电常数（高kappa）材料的设备和方法。该方法的一个实施方案是通过在单独的步骤中使用两种蚀刻气体化学物质来蚀刻层而实现的。为了突破高介电常数材料的蚀刻，第一蚀刻气体化学物质不含氧气，以防止从先前的多晶硅蚀刻工艺留下的任何残留物导致较低的高卡宾脚，并且还控制与底层氧化硅层。第二种过蚀刻气体化学提供了高氧化硅材料上的高介电常数材料的高蚀刻选择性，以与低源功率组合以进一步减少硅衬底氧化问题。

5. 发明申请

US20080057729A1 ETCH METHODS TO FORM ANISOTROPIC FEATURES FOR HIGH ASPECT RATIO APPLICATIONS 审中-公开
标题翻译： ETCH方法形成高度比例应用的各向异性特征
公开(公告)号：US20080057729A1
公开(公告)日：2008-03-06
申请号：US11926531
申请日：2007-10-29
申请人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
发明人： Meihua Shen , Uwe Leucke , Guangxiang Jin , Xikun Wang , Wei Liu , Scott Williams
IPC分类号： H01L21/465
CPC分类号： H01L21/76802 , H01L21/32137 , H01L21/76814
摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
摘要翻译：在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面层。

6. 发明授权

US09533332B2 Methods for in-situ chamber clean utilized in an etching processing chamber 有权
标题翻译：在蚀刻处理室中利用原位室清洁的方法
公开(公告)号：US09533332B2
公开(公告)日：2017-01-03
申请号：US13614365
申请日：2012-09-13
申请人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
发明人： Noel Sun , Meihua Shen , Nicolas Gani , Chung Nang Liu , Radhika C. Mani
IPC分类号： B08B5/00 , B08B7/00 , B08B9/08 , C23C16/44 , H01J37/32
CPC分类号： B08B5/00 , B08B7/0035 , C23C16/4405 , H01J37/32449 , H01J37/32862 , Y10S438/905
摘要： Embodiments of the invention include methods for in-situ chamber dry cleaning a plasma processing chamber utilized for gate structure fabrication process in semiconductor devices. In one embodiment, a method for in-situ chamber dry clean includes supplying a first cleaning gas including at least a boron containing gas into a processing chamber in absence of a substrate disposed therein, supplying a second cleaning gas including at least a halogen containing gas into the processing chamber in absence of the substrate, and supplying a third cleaning gas including at least an oxygen containing gas into the processing chamber in absence of the substrate.
摘要翻译：本发明的实施例包括用于半导体器件中用于栅极结构制造工艺的等离子体处理室的原位室干洗的方法。在一个实施例中，一种用于原位室干洗的方法包括在不存在设置在其中的基板的情况下将包括至少含硼气体的第一清洁气体供应到处理室中，提供至少包含含卤素气体的第二清洁气体在没有基板的情况下进入处理室，并且在没有基板的情况下将至少包含含氧气体的第三清洁气体供应到处理室中。

7. 发明授权

US07780862B2 Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
标题翻译：用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法
公开(公告)号：US07780862B2
公开(公告)日：2010-08-24
申请号：US11386054
申请日：2006-03-21
申请人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
发明人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116
摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
摘要翻译：在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片室到第一等离子体室，而不破坏真空。在第一室中以低阴极温度蚀刻下导电材料层。在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

8. 发明申请

US20100210112A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A LANTHANUM-FAMILY-BASED OXIDE LAYER 失效
标题翻译：用于制备具有基于民族的氧化物层的半导体器件的方法
公开(公告)号：US20100210112A1
公开(公告)日：2010-08-19
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/3065
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

9. 发明申请

US20090004875A1 METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE 审中-公开
标题翻译：用于形成基底上超薄结构的非晶碳膜的方法
公开(公告)号：US20090004875A1
公开(公告)日：2009-01-01
申请号：US12163888
申请日：2008-06-27
申请人： Meihua Shen , Diana Xiaobing Ma , Wendy H. Yeh , Kenneth MacWilliams , Wei Liu , Thorsten B. Lill
发明人： Meihua Shen , Diana Xiaobing Ma , Wendy H. Yeh , Kenneth MacWilliams , Wei Liu , Thorsten B. Lill
IPC分类号： H01L21/308
CPC分类号： H01L21/0337
摘要： Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer.
摘要翻译：提供了使用包括在蚀刻处理期间修整掩模层的方法来形成超薄结构的方法。本文描述的实施例可有利地用于在临界尺寸小于55nm及以上的衬底上制造亚微米结构。在一个实施例中，在衬底上形成亚微米结构的方法可以包括提供具有设置在膜堆叠上的图案化光致抗蚀剂层进入蚀刻室的衬底，其中所述膜堆叠包括至少设置在下层上的硬掩模层，将光致抗蚀剂层修剪到第一预定临界尺寸，通过由修剪的光致抗蚀剂层限定的开口蚀刻硬掩模层，将硬掩模层修剪到第二预定临界尺寸，以及通过由修剪的硬掩模层限定的开孔蚀刻下层。

10. 发明申请

US20090004870A1 METHODS FOR HIGH TEMPERATURE ETCHING A HIGH-K MATERIAL GATE STRUCTURE 失效
标题翻译：高温蚀刻高K材料门结构的方法
公开(公告)号：US20090004870A1
公开(公告)日：2009-01-01
申请号：US12146303
申请日：2008-06-25
申请人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
发明人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/28282 , H01L21/31116 , H01L21/31122 , H01L21/32137
摘要： Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.
摘要翻译：提供了在高温下蚀刻高k材料的方法。在一个实施例中，在衬底上蚀刻高k材料的方法可以包括提供其上设置有高k材料层的衬底到蚀刻室中，从包括至少含卤素气体的蚀刻气体混合物形成等离子体到蚀刻室，在蚀刻室的内部表面的温度保持超过约100摄氏度，同时在存在等离子体的同时蚀刻高k材料层，并将衬底温度保持在约100摄氏度至约250度之间摄氏度，同时在存在等离子体的同时蚀刻高k材料层。

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