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    • 2. 发明授权
    • Method and system for reliably defining and determining timeout values in unreliable datagrams
    • 用于在不可靠数据报中可靠地定义和确定超时值的方法和系统
    • US06748559B1
    • 2004-06-08
    • US09692349
    • 2000-10-19
    • Gregory Francis PfisterGiles Roger FrazierDanny Marvin NealSteven Mark Thurber
    • Gregory Francis PfisterGiles Roger FrazierDanny Marvin NealSteven Mark Thurber
    • G06F1100
    • H04L41/00H04L41/046H04L41/0806H04L41/082H04L41/12H04L43/0852
    • A method for managing allocation of network resources within the distributed computer system is provided. Specifically, the network traversal time and the end node response time for requests and/or packets being routed in a switch-connected system area network are utilized to determine the total round trip time for completion of the particular network operation. The sum of the timeout values for all switches that participate in routing the request from a requester (source) to the receptor node (target) is provided to the requester's channel adapter (CA). The time-out values are provided by the switch manufacturer and are sent to a network Subnet Manager (SM) via SM packets (SMP). The timeout values added together represent the SubnetTimeout. The time-out value of the target channel adapter (CA), the ResponseTime, is also provided to the requester. The requester then utilizes one of two timeout equations to calculate the overall response time required for the request to be completed. A timer is started and the elapsed time to complete the request is monitored and compared with the overall response time calculated. When the timer expires before a response is received at the requester, the operation is assumed to have failed and the network resources being utilized by the request may be reallocated to another network operation.
    • 提供了一种管理分布式计算机系统内网络资源分配的方法。 具体地,利用在交换机连接的系统区域网络中路由的请求和/或分组的网络遍历时间和终止节点响应时间来确定完成特定网络操作的总往返时间。 参与将请求从请求者(源)路由到接收节点(目标)的所有交换机的超时值的总和提供给请求者的信道适配器(CA)。 超时值由交换机制造商提供,并通过SM数据包(SMP)发送到网络子网管理器(SM)。 添加的超时值表示SubnetTimeout。 目标通道适配器(CA)的超时值ResponseTime也提供给请求者。 然后,请求者使用两个超时方程之一来计算请求完成所需的总体响应时间。 启动定时器,并监视完成请求的经过时间,并与计算的总响应时间进行比较。 当定时器在请求者接收到响应之前到期时,假设该操作已经失败,并且该请求所利用的网络资源可能被重新分配到另一个网络操作。
    • 3. 发明授权
    • Method and apparatus for reliably choosing a master network manager during initialization of a network computing system
    • 在网络计算系统的初始化期间可靠地选择主网络管理器的方法和装置
    • US06941350B1
    • 2005-09-06
    • US09692346
    • 2000-10-19
    • Giles Roger FrazierGregory Francis PfisterSteven Mark ThurberDono Van-Mierop
    • Giles Roger FrazierGregory Francis PfisterSteven Mark ThurberDono Van-Mierop
    • G06F15/16G06F15/173
    • G06F15/17375H04L63/061
    • A method in a node within network computing system for selecting a master network manager, wherein the first node is associated with a first priority. Requests are sent to the network computing system to discover other nodes within the network computing system. A second priority from the request is identified in response to receiving a response to one of the requests from another node within the network computing system. The first node shifts to a standby mode if it discovers a master subnet manager or the second priority is higher than the first priority. The first node shifts to a master mode if a response containing a priority higher than the first priority is absent in responses received by the first node and the first node has completed checking all other nodes in the network computing system. In the case where the priority received is equal, the comparison is further made on the globally unique identifier which is received from the same node, in which case the node with the lowest globally unique identifier wins the arbitration.
    • 网络计算系统内用于选择主网络管理器的节点中的方法,其中所述第一节点与第一优先级相关联。 将请求发送到网络计算系统以发现网络计算系统内的其他节点。 响应于响应于来自网络计算系统内的另一个节点的一个请求的响应来识别来自请求的第二优先级。 如果发现主子网管理器或第二优先级高于第一优先级,则第一节点转移到待机模式。 如果在由第一节点接收的响应中缺少包含高于第一优先级的优先级的响应,则第一节点转移到主模式,并且第一节点已经完成了对网络计算系统中的所有其他节点的检查。 在接收到的优先级相等的情况下,进一步对从同一节点接收到的全局唯一标识符进行比较,在这种情况下,具有最低全局唯一标识符的节点赢得仲裁。
    • 5. 发明授权
    • Method and system for choosing a queue protection key that is tamper-proof from an application
    • 从应用程序中选择防篡改的队列保护密钥的方法和系统
    • US06851059B1
    • 2005-02-01
    • US09692353
    • 2000-10-19
    • Gregory Francis PfisterRenato John RecioDanny Marvin NealSteven Mark Thurber
    • Gregory Francis PfisterRenato John RecioDanny Marvin NealSteven Mark Thurber
    • H04L9/00H04L29/06
    • H04L63/06
    • A method for enabling a Q_key that is tamper proof from applications on a distributed computer system to protect selected network operations is provided. Applications and an operating system (OS) execute on the end nodes and each may access various network resources. In the invention, the network resources are configured for selective access by particular applications or OS.In a preferred embodiment, a control bit of a Q_key, which allows applications to authenticate their use of particular communication resources, i.e., the send and receive queues, is reserved and utilized to signal whether a particular application is allowed access to the resources. Setting the control bit to 0 allows the Q_key to be set by an application directly. When the control bit is set to 1, the Q_key cannot be set by an application and can only be set using a privileged operation performed only by the OS.
    • 提供了一种用于启用防止来自分布式计算机系统上的应用程序的防篡改的Q_key以保护所选网络操作的方法。 应用和操作系统(OS)在终端节点上执行,每个可以访问各种网络资源。 在本发明中,网络资源被配置用于特定应用或OS的选择性访问。在优选实施例中,Q_key的控制位允许应用程序认证其对特定通信资源的使用,即发送和接收队列, 被保留并用于发出特定应用是否被允许访问资源。 将控制位设置为0允许应用程序直接设置Q_key。 当控制位设置为1时,Q_key不能由应用程序设置,只能使用仅由操作系统执行的特权操作进行设置。
    • 6. 发明授权
    • DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge
    • 使用设备仲裁级别在LPAR环境中DMA窗口,以允许每个终端桥接多个IOA
    • US06823404B2
    • 2004-11-23
    • US09766764
    • 2001-01-23
    • Richard Louis ArndtDanny Marvin NealSteven Mark Thurber
    • Richard Louis ArndtDanny Marvin NealSteven Mark Thurber
    • G06F300
    • G06F13/28
    • A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.
    • 用于防止在逻辑分区的数据处理系统中由操作系统(OS)映像使用的输入/输出(I / O)适配器的方法,系统和装置从分配给另一个OS映像的存储器位置获取或破坏数据 在数据处理系统内提供。 虚拟机管理程序防止在直接存储器访问(DMA)操作期间通过分配每个输入/输出适配器一个I / O范围的逻辑分区之一和分配给其他逻辑分区的存储器位置之间的输入/输出适配器之间的数据传输 总线DMA地址。 I / O适配器(IOA)通过终端桥连接到PCI主机桥。 单个终端桥可以支持多个IOA,在这种情况下,每个终端桥具有多组范围寄存器,每个范围寄存器与其所连接的IOA中的相应一个相关联。 提供了一个仲裁器,其选择一个输入/输出适配器来使用PCI总线。 终端桥可以检查从仲裁器到IOA的授权信号,以确定要使用哪个范围寄存器组。
    • 7. 发明授权
    • Coherency for DMA read cached data
    • DMA读取缓存数据的一致性
    • US06636947B1
    • 2003-10-21
    • US09645177
    • 2000-08-24
    • Danny Marvin NealSteven Mark Thurber
    • Danny Marvin NealSteven Mark Thurber
    • G06F1212
    • G06F12/0817G06F2212/621
    • A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.
    • 提供了一种方法和实现的计算机系统,其使得能够实现用于桥接缓存数据的一致性系统的过程,所述数据由通常在系统一致性域外的适配器和适配器桥接电路访问。 扩展架构包括一个或多个主机桥。 主桥中的至少一个通过下层总线到总线桥和一个或多个I / O总线耦合到I / O适配器设备。 主机桥保持缓冲区一致性目录,当Host Bridge接收到Invalidate命令时,将标识包含引用数据的桥接缓冲区,并指示数据无效。
    • 9. 发明授权
    • System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer
    • 即使当前信息传送请求超过传送缓冲器的当前可用容量时,也执行当前信息传送请求的系统
    • US06457077B1
    • 2002-09-24
    • US09329459
    • 1999-06-10
    • Richard A. KelleyDanny Marvin NealSteven Mark ThurberAdalberto Guillermo Yanes
    • Richard A. KelleyDanny Marvin NealSteven Mark ThurberAdalberto Guillermo Yanes
    • G06F1314
    • G06F13/4059
    • A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.
    • 提供了一种方法和实现系统,其中系统桥电路能够执行或过度提交来自用于信息传输的系统设备的事务请求,该信息传输超过桥电路的当前容量,以便在从指定目标返回时接收所请求的信息 设备如系统内存或其他系统设备。 交易请求沿着数据路径移动到指定的目标设备,并且所请求的信息在示例中返回到请求设备。 当所请求的信息被返回到请求桥接电路时,多个保持缓冲器通常已经被释放并且可用于接受并将该信息传递给请求设备。 在所示实施例中,过度承诺的量是可编程的,并且可以自动调整对交易请求的过度承诺的量,以根据特定系统需求和当前数据传输流量水平优化信息传递。
    • 10. 发明授权
    • Buffer assignment for bridges
    • 桥梁缓冲区分配
    • US06421756B1
    • 2002-07-16
    • US09306200
    • 1999-05-06
    • Richard A. KelleyDanny Marvin NealSteven Mark Thurber
    • Richard A. KelleyDanny Marvin NealSteven Mark Thurber
    • G06F1340
    • G06F13/4031G06F13/4059
    • A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.
    • 提供了一种方法和实现的计算机系统,其中桥接缓冲器被组合在一起在池中,并且在信息传输期间根据需要被动态分配和未分配给适配器设备。 在示例性外围组件互连(PCI)系统实施例中,PCI主机桥(PHB)被耦合到第一PCI总线,并且第一PCI总线的设备中的一个被PCI-PCI桥(PPB)占用,PCI桥PCI 第一个PCI总线到第二个PCI总线。 相对于直接和间接连接到第一PCI总线的PCI设备的数量,PHB中的PHB缓冲器的分配。 在第一和第二PCI总线上的设备在缓冲区分配过程中被赋予大致相等的状态。 在完成到任何一个适配器的数据传输之后,分配给该特定适配器的释放缓冲区根据需要动态地重新分配给其他适配器,以优化PHB池中所有缓冲区的使用。