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1. 发明申请

US20050041503A1 Non-volatile memory having a reference transistor 有权
标题翻译：具有参考晶体管的非易失性存储器
公开(公告)号：US20050041503A1
公开(公告)日：2005-02-24
申请号：US10950855
申请日：2004-09-27
申请人： Gowrishankar Chindalore , Rajesh Rao , Jane Yater
发明人： Gowrishankar Chindalore , Rajesh Rao , Jane Yater
IPC分类号： G11C5/00 , G11C16/28 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/28 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

2. 发明申请

US20050007820A1 VARIABLE GATE BIAS FOR A REFERENCE TRANSISTOR IN A NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器中的参考晶体管的可变栅极偏置
公开(公告)号：US20050007820A1
公开(公告)日：2005-01-13
申请号：US10609359
申请日：2003-06-27
申请人： Gowrishankar Chindalore , Rajesh Rao , Jane Yater
发明人： Gowrishankar Chindalore , Rajesh Rao , Jane Yater
IPC分类号： G11C20060101 , G11C11/34 , G11C16/00 , G11C16/06 , G11C16/28 , H01L21/28 , H01L21/8247
CPC分类号： B82Y10/00 , G11C16/28 , G11C2216/06 , H01L21/28273 , H01L27/11531
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

3. 发明申请

US20070019472A1 Electronic device including a memory array and conductive lines 有权
标题翻译：电子设备包括存储器阵列和导线
公开(公告)号：US20070019472A1
公开(公告)日：2007-01-25
申请号：US11188898
申请日：2005-07-25
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

4. 发明授权

US07642163B2 Process of forming an electronic device including discontinuous storage elements within a dielectric layer 有权
标题翻译：在电介质层内形成包括不连续存储元件的电子器件的工艺
公开(公告)号：US07642163B2
公开(公告)日：2010-01-05
申请号：US11693829
申请日：2007-03-30
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Gowrishankar Chindalore , David Sing , Jane Yater
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Gowrishankar Chindalore , David Sing , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.
摘要翻译：电子设备可以包括在电介质层内具有DSE的非易失性存储单元。一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

5. 发明申请

US20080242022A1 ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS WITHIN A DIELECTRIC LAYER AND PROCESS OF FORMING THE ELECTRONIC DEVICE 有权
标题翻译：在电介质层中包括不连续存储元件的电子器件和形成电子器件的工艺
公开(公告)号：US20080242022A1
公开(公告)日：2008-10-02
申请号：US11693829
申请日：2007-03-30
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Gowrishankar Chindalore , David Sing , Jane Yater
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar , Gowrishankar Chindalore , David Sing , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.
摘要翻译：电子设备可以包括在电介质层内具有DSE的非易失性存储单元。一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

6. 发明申请

US20080019178A1 ELECTRONIC DEVICE INCLUDING A MEMORY ARRAY AND CONDUCTIVE LINES 有权
标题翻译：包括记忆阵列和导电线的电子设备
公开(公告)号：US20080019178A1
公开(公告)日：2008-01-24
申请号：US11834391
申请日：2007-08-06
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

7. 发明申请

US20060079051A1 METHOD FOR FORMING A MULTI-BIT NON-VOLATILE MEMORY DEVICE 有权
标题翻译：用于形成多位非易失性存储器件的方法
公开(公告)号：US20060079051A1
公开(公告)日：2006-04-13
申请号：US10961014
申请日：2004-10-08
申请人： Gowrishankar Chindalore , Jane Yater
发明人： Gowrishankar Chindalore , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions. This device may be used, for example, in a VGA memory array.
摘要翻译：形成非易失性存储器件包括提供半导体衬底，形成具有覆盖半导体衬底的第一多个开口的掩模层，在由掩模层确定的位置处在半导体衬底中形成扩散区，在第一多个的开口，去除所述掩模层以形成第二多个开口，沿着所述第二多个开口的边缘并且邻近所述电介质形成牺牲隔离物，形成分离电介质以在所述第二多个开口的每一个内分离所述牺牲隔离物，形成覆盖所述分离电介质的牺牲保护层，去除所述牺牲隔离物，去除所述牺牲保护层，在所述第二多个开口的每一个内形成至少两个存储器存储区域，以及形成覆盖所述至少两个存储器存储器地区。该装置可以用于例如VGA存储器阵列中。

8. 发明申请

US20070018229A1 Electronic device including discontinuous storage elements and a process for forming the same 有权
公开(公告)号：US20070018229A1
公开(公告)日：2007-01-25
申请号：US11188953
申请日：2005-07-25
申请人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
发明人： Jane Yater , Gowrishankar Chindalore , Cheong Hong
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C16/0491 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.

9. 发明申请

US20050191808A1 Method for removing nanoclusters from selected regions 失效
标题翻译：从选定区域去除纳米团簇的方法
公开(公告)号：US20050191808A1
公开(公告)日：2005-09-01
申请号：US10787510
申请日：2004-02-26
申请人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
发明人： Robert Steimle , Jane Yater , Gowrishankar Chindalore , Craig Swift , Steven Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.
摘要翻译：纳米簇被覆盖在集成电路上，然后从不需要纳米团簇的区域去除。在毛毯沉积之前在纳米团簇不需要的那些区域中形成牺牲层。然后去除纳米团簇和牺牲层。在一种形式中，牺牲层包括沉积的含氮化物或含氧化物层。或者，牺牲层包括先前用于在衬底中形成隔离区域的衬垫氧化物或衬垫氮化物层中的至少一个。然后可以将纳米簇装置和非纳群集装置集成到相同的集成电路上。牺牲层的使用保护下层，从而防止随后形成的非纳群集装置的性能下降。

10. 发明申请

US20060194438A1 METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE 有权
标题翻译：形成纳米碳管充电储存装置的方法
公开(公告)号：US20060194438A1
公开(公告)日：2006-08-31
申请号：US10876820
申请日：2004-06-25
申请人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
发明人： Rajesh Rao , Ramachandran Muralidhar , Robert Steimle , Gowrishankar Chindalore
IPC分类号： H01L21/302 , H01L31/112 , H01L21/36
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译：通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。第二形成的含多晶硅的层从包含多个存储单元的区域中去除。在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

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