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    • 1. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20070051997A1
    • 2007-03-08
    • US11218184
    • 2005-08-31
    • Gordon HallerSanh TangSteve Cummings
    • Gordon HallerSanh TangSteve Cummings
    • H01L29/94H01L21/8242
    • H01L21/823487H01L27/10817H01L27/10823H01L27/10876H01L27/10888
    • A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    • 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触,所以可以减少多个制造步骤,并且还可以减少制造缺陷的可能性。 在一些实施例中,存储器件可以包括垂直晶体管,其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域,栅极区域与源极/漏极区域进一步间隔开,因此,可以减小栅极区域和源极/漏极区域之间的交叉电容。
    • 2. 发明授权
    • Methods of fabricating a memory device
    • 制造存储器件的方法
    • US08222105B2
    • 2012-07-17
    • US12703502
    • 2010-02-10
    • Gordon HallerSanh D. TangSteve Cummings
    • Gordon HallerSanh D. TangSteve Cummings
    • H01L29/94
    • H01L21/823487H01L27/10817H01L27/10823H01L27/10876H01L27/10888
    • A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    • 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触,所以可以减少多个制造步骤,并且还可以减少制造缺陷的可能性。 在一些实施例中,存储器件可以包括垂直晶体管,其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域,栅极区域与源极/漏极区域进一步间隔开,因此,可以减小栅极区域和源极/漏极区域之间的交叉电容。
    • 3. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07696567B2
    • 2010-04-13
    • US11218184
    • 2005-08-31
    • Gordon HallerSanh Dang TangSteve Cummings
    • Gordon HallerSanh Dang TangSteve Cummings
    • H01L29/94
    • H01L21/823487H01L27/10817H01L27/10823H01L27/10876H01L27/10888
    • A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    • 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触,所以可以减少多个制造步骤,并且还可以减少制造缺陷的可能性。 在一些实施例中,存储器件可以包括垂直晶体管,其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域,栅极区域与源极/漏极区域进一步间隔开,因此,可以减小栅极区域和源极/漏极区域之间的交叉电容。
    • 4. 发明申请
    • Semiconductor Memory Device
    • 半导体存储器件
    • US20100144107A1
    • 2010-06-10
    • US12703502
    • 2010-02-10
    • Gordon HallerSanh Dang TangSteve Cummings
    • Gordon HallerSanh Dang TangSteve Cummings
    • H01L21/8242
    • H01L21/823487H01L27/10817H01L27/10823H01L27/10876H01L27/10888
    • A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.
    • 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触,所以可以减少多个制造步骤,并且还可以减少制造缺陷的可能性。 在一些实施例中,存储器件可以包括垂直晶体管,其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域,栅极区域与源极/漏极区域进一步间隔开,因此,可以减小栅极区域和源极/漏极区域之间的交叉电容。
    • 8. 发明申请
    • Ice fishing device
    • 冰钓设备
    • US20100242337A1
    • 2010-09-30
    • US12384020
    • 2009-03-30
    • Steve Cummings
    • Steve Cummings
    • A01K97/01A01K97/00A01K85/01
    • A01K97/01
    • An ice fishing hole lighting device has a solid frame with an opening within the frame having an average diameter of at least six inches. The frame has a top portion and a bottom portion, the bottom portion of the frame having a flat surface so as to lay against surfaces of ice, the bottom of the frame having between 2 and 12 high efficiency light emitting devices that emit light from the bottom portion of the frame without extending beyond the flat surface to interrupt contact between the flat surface and the ice surface. There are leads from the lights to a battery storage area, and a battery is in the battery storage area.
    • 冰钓鱼眼照明装置具有在框架内具有平均直径至少为六英寸的开口的实心框架。 框架具有顶部和底部,框架的底部具有平坦的表面以便抵靠冰面,该框架的底部具有2至12个高效率的发光装置,其从 框架的底部部分不延伸超过平坦表面以中断平坦表面和冰面之间的接触。 灯具有电源线到电池存储区域,电池位于电池存储区域。