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1. 发明申请

US20070224826A1 Plasma dielectric etch process including in-situ backside polymer removal for low-dielectric constant material 失效
标题翻译：等离子体电介质蚀刻工艺，包括用于低介电常数材料的原位背面聚合物去除
公开(公告)号：US20070224826A1
公开(公告)日：2007-09-27
申请号：US11386428
申请日：2006-03-22
申请人： Gerardo Delgadino , Richard Hagborg , Douglas Buchberger
发明人： Gerardo Delgadino , Richard Hagborg , Douglas Buchberger
IPC分类号： H01L21/461 , C23F1/00 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/0209 , H01L21/31138 , H01L21/76814
摘要： A plasma etch process with in-situ backside polymer removal begins with a workpiece having a porous or non-porous carbon-doped silicon oxide dielectric layer and a photoresist mask on a surface of the workpiece. The workpiece is clamped onto an electrostatic chuck in an etch reactor chamber. The process includes introducing a fluoro-carbon based process gas and applying RF bias power to the electrostatic chuck and RF source power to an overhead electrode to etch exposed portions of the dielectric layer while depositing protective fluoro-carbon polymer on the photoresist mask. The process further includes removing the fluoro-carbon based process gas and introducing a hydrogen-based process gas and applying RF source power to the overhead electrode. The lift pins in the electrostatic chuck are extended to raise the workpiece above the electrostatic chuck and expose a backside of the workpiece to plasma in the reactor chamber, so as to reduce polymer previously deposited on the backside, until the polymer has been removed from the backside.
摘要翻译：具有原位背面聚合物去除的等离子体蚀刻工艺开始于在工件的表面上具有多孔或非多孔碳掺杂氧化硅介电层和光致抗蚀剂掩模的工件。将工件夹在蚀刻反应器室中的静电卡盘上。该方法包括引入基于氟碳的工艺气体并将RF偏压功率施加到静电吸盘和RF源功率到顶置电极以蚀刻介电层的暴露部分，同时在光致抗蚀剂掩模上沉积保护性氟碳聚合物。该方法还包括除去基于氟碳的工艺气体并引入基于氢的工艺气体并将RF源功率施加到顶置电极。静电卡盘中的提升销被延伸以使工件在静电卡盘上方升高，并将工件的背面暴露在反应器室中的等离子体中，以便减少先前沉积在背面的聚合物，直到聚合物从背面。

2. 发明申请

US20130126476A1 DUAL ZONE TEMPERATURE CONTROL OF UPPER ELECTRODES 有权
标题翻译：上电极双区温度控制
公开(公告)号：US20130126476A1
公开(公告)日：2013-05-23
申请号：US13420949
申请日：2012-03-15
申请人： Alexei Marakhtanov , Rajinder Dhindsa , Ryan Bise , Lumin Li , Sang Ki Nam , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony de la LIera
发明人： Alexei Marakhtanov , Rajinder Dhindsa , Ryan Bise , Lumin Li , Sang Ki Nam , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony de la LIera
IPC分类号： C23F1/00 , C23F1/08
CPC分类号： H01J37/32642 , H01J37/3244 , H01J37/32541 , H01J37/32724 , H01L21/67109
摘要： A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber.
摘要翻译：等离子体处理的系统和方法包括等离子体室，其包括基板支撑件和与基板支撑件相对的上电极，上电极具有多个同心温度控制区域和耦合到等离子体室的控制器。

3. 发明申请

US20070224827A1 Methods for etching a bottom anti-reflective coating layer in dual damascene application 审中-公开
标题翻译：在双镶嵌应用中蚀刻底部抗反射涂层的方法
公开(公告)号：US20070224827A1
公开(公告)日：2007-09-27
申请号：US11388232
申请日：2006-03-22
申请人： Ying Xiao , Gerardo Delgadino , Karsten Schneider
发明人： Ying Xiao , Gerardo Delgadino , Karsten Schneider
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76808 , H01L21/31138
摘要： Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a first portion of the BARC layer filling in the vias, and supplying a second gas mixture comprising NH3 gas into the reactor to etch a second portion of the BARC layer disposed in the vias.
摘要翻译：提供了在双镶嵌结构中两步蚀刻BARC层的方法。在一个实施例中，该方法包括在蚀刻反应器中提供具有填充有设置在衬底上的BARC层的通孔的衬底，将第一气体混合物供应到反应器中以蚀刻填充在通孔中的BARC层的第一部分，包含NH 3气体的第二气体混合物进入反应器以蚀刻设置在通孔中的BARC层的第二部分。

4. 发明申请

US20130126486A1 Multi Zone Gas Injection Upper Electrode System 审中-公开
标题翻译：多区域注气上电极系统
公开(公告)号：US20130126486A1
公开(公告)日：2013-05-23
申请号：US13438473
申请日：2012-04-03
申请人： Ryan Bise , Rajinder Dhindsa , Alexei Marakhtanov , Lumin Li , Sang Ki Naw , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony Dela Llera , Darrell Ehrlich
发明人： Ryan Bise , Rajinder Dhindsa , Alexei Marakhtanov , Lumin Li , Sang Ki Naw , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony Dela Llera , Darrell Ehrlich
IPC分类号： B23K9/00
CPC分类号： H01J37/32642 , H01J37/3244 , H01J37/32541 , H01J37/32724 , H01L21/67109
摘要： A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.
摘要翻译：等离子体处理的系统和方法包括等离子体处理系统，其包括等离子体室和耦合到等离子体室的控制器。等离子体室包括基板支撑件和与基板支撑件相对的上电极，上电极具有多个同心气体注入区域。

5. 发明申请

US20070026665A1 METHOD OF FABRICATING A DUAL DAMASCENE INTERCONNECT STRUCTURE 审中-公开
标题翻译：双重DAMASCENE互连结构的制作方法
公开(公告)号：US20070026665A1
公开(公告)日：2007-02-01
申请号：US11535935
申请日：2006-09-27
申请人： Kallol Bera , Gerardo Delgadino , Allen Zhao , Yan Ye
发明人： Kallol Bera , Gerardo Delgadino , Allen Zhao , Yan Ye
IPC分类号： H01L21/4763 , H01L21/461 , H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76808
摘要： A method of fabricating a dual damascene interconnect structure uses a very high frequency high-density plasma and selectively controlled substrate bias for in-situ etching a trench above a via hole of the interconnect structure and a barrier layer between the via hole and underlying conductive layer.
摘要翻译：制造双镶嵌互连结构的方法使用非常高频的高密度等离子体和选择性控制的衬底偏压，用于原位蚀刻互连结构的通孔上方的沟槽以及通孔和下面的导电层之间的阻挡层。

6. 发明申请

US20050059234A1 Method of fabricating a dual damascene interconnect structure 审中-公开
标题翻译：制造双镶嵌互连结构的方法
公开(公告)号：US20050059234A1
公开(公告)日：2005-03-17
申请号：US10663304
申请日：2003-09-16
申请人： Kallol Bera , Gerardo Delgadino , Allen Zhao , Yan Ye
发明人： Kallol Bera , Gerardo Delgadino , Allen Zhao , Yan Ye
IPC分类号： H01L21/311 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76808
摘要： A method of fabricating a dual damascene interconnect structure uses a very high frequency high-density plasma and selectively controlled substrate bias for in-situ etching a trench above a via hole of the interconnect structure and a barrier layer between the via hole and underlying conductive layer.
摘要翻译：制造双镶嵌互连结构的方法使用非常高频的高密度等离子体和选择性控制的衬底偏压，用于原位蚀刻互连结构的通孔上方的沟槽，以及通孔和下面的导电层之间的阻挡层。

7. 发明授权

US10622195B2 Multi zone gas injection upper electrode system 有权
公开(公告)号：US10622195B2
公开(公告)日：2020-04-14
申请号：US13438473
申请日：2012-04-03
申请人： Ryan Bise , Rajinder Dhindsa , Alexei Marakhtanov , Lumin Li , Sang Ki Nam , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony Dela Llera , Darrell Ehrlich
发明人： Ryan Bise , Rajinder Dhindsa , Alexei Marakhtanov , Lumin Li , Sang Ki Nam , Jim Rogers , Eric Hudson , Gerardo Delgadino , Andrew D. Bailey, III , Mike Kellogg , Anthony Dela Llera , Darrell Ehrlich
IPC分类号： B23K9/00 , H01J37/32 , H01L21/67
CPC分类号： H01J37/32642 , H01J37/3244 , H01J37/32541 , H01J37/32724 , H01L21/67109
摘要： A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.

8. 发明申请

US20070224807A1 Methods for etching a dielectric barrier layer with high selectivity 失效
标题翻译：用于以高选择性蚀刻电介质阻挡层的方法
公开(公告)号：US20070224807A1
公开(公告)日：2007-09-27
申请号：US11388246
申请日：2006-03-22
申请人： Ying Xiao , Gerardo Delgadino , Karsten Schneider
发明人： Ying Xiao , Gerardo Delgadino , Karsten Schneider
IPC分类号： H01L21/465
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76814
摘要： Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H2 gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.
摘要翻译：提供了对绝缘体绝缘层具有高选择性的蚀刻电介质阻挡层的方法。在一个实施例中，该方法包括提供一个衬底，该衬底具有通过反应器中的电介质体绝缘层暴露的介电阻挡层的一部分，使包含H 2气体，含氟气体的气体混合物在至少插入气体进入反应器，并且将电介质阻挡层的暴露部分选择性地蚀刻到介电体绝缘层。

9. 发明申请

US20060118519A1 Dielectric etch method with high source and low bombardment plasma providing high etch rates 审中-公开
标题翻译：具有高源和低轰击等离子体的介电蚀刻方法提供高蚀刻速率
公开(公告)号：US20060118519A1
公开(公告)日：2006-06-08
申请号：US11003227
申请日：2004-12-03
申请人： Gerardo Delgadino , Chang-Lin Hsieh , Yan Ye , Hyunjong Shim
发明人： Gerardo Delgadino , Chang-Lin Hsieh , Yan Ye , Hyunjong Shim
IPC分类号： C23F1/00 , B44C1/22 , C03C25/68 , H01L21/461
CPC分类号： H01L21/31116 , C09K13/00 , H01L21/31122
摘要： In at least some embodiments, the present invention is a plasma etching method which includes applying a gas mixture comprising CF4, N2 and Ar and forming a high density and low bombardment energy plasma. The high density and low bombardment energy plasma is formed by using high source and low bias power settings. The gas mixture can further include H2, NH3, a hydrofluorocarbon gas and/or a fluorocarbon gas. The hydrofluorocarbon gas can include CH2F2, CH3F; and/or CHF3. The fluorocarbon gas can include C4F8, C4F6 and/or C5F8.
摘要翻译：在至少一些实施方案中，本发明是等离子体蚀刻方法，其包括施加包含CF 4 N 2，N 2和Ar的气体混合物并形成高密度和低轰击能量等离子体高密度和低轰击能量等离子体通过使用高源和低偏压功率设置形成。气体混合物可以进一步包括H 2 CO 3，NH 3，氢氟烃气体和/或碳氟化合物气体。氢氟烃气体可以包括CH 2 2 F 2 CH 3，CH 3 F; 和/或CHF 3。碳氟化合物气体可以包括C 4 C 8 C 6，C 4 F 6和/或C 5 8 。

10. 发明授权

US08652298B2 Triode reactor design with multiple radiofrequency powers 有权
标题翻译：具有多个射频功率的三极管反应器设计
公开(公告)号：US08652298B2
公开(公告)日：2014-02-18
申请号：US13301725
申请日：2011-11-21
申请人： Rajinder Dhindsa , Alexei Marakhtanov , Gerardo Delgadino , Eric Hudson , Bi Ming Yen , Andrew D. Bailey, III
发明人： Rajinder Dhindsa , Alexei Marakhtanov , Gerardo Delgadino , Eric Hudson , Bi Ming Yen , Andrew D. Bailey, III
IPC分类号： C23F1/00
CPC分类号： H01J37/32091 , H01J37/32165
摘要： Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.
摘要翻译：提供了半导体制造方法，系统和计算机程序。一个晶片处理装置包括：顶部电极; 底部电极; 第一射频（RF）电源; 第二RF电源; 第三射频电源; 第四RF电源; 和开关。第一，第二和第三电源耦合到底部电极。此外，开关可操作为处于第一位置或第二位置之一，其中第一位置使顶部电极连接到地，而第二位置使顶部电极连接到第四RF电源。

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