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1. 发明授权

US4013483A Method of adjusting the threshold voltage of field effect transistors 失效
标题翻译：调整场效应晶体管阈值电压的方法
公开(公告)号：US4013483A
公开(公告)日：1977-03-22
申请号：US598165
申请日：1975-07-22
申请人： Gerard Nuzillat , Christian Arnado
发明人： Gerard Nuzillat , Christian Arnado
IPC分类号： H01L29/80 , H01L21/00 , H01L21/265 , H01L21/337 , H01L21/338 , H01L29/808 , H01L29/812
CPC分类号： H01L29/812 , H01L21/00 , H01L21/2652 , H01L29/808
摘要： A method of adjusting the threshold voltages of field effect transistors, in particular of SCHOTTKY gate field-effect transistors, is provided. During the process of manufacture of the transistor, the channel charge carrier density is modified by ion implantation. A monitoring device, in the form of a test transistor, is manufactured at the same time as the production transistors and on the same wafer thereas. An appendix of the test transistor makes it possible to measure the threshold voltage and saturation current, during ionic implantation.
摘要翻译：提供了调整场效应晶体管，特别是SCHOTTKY栅场效应晶体管的阈值电压的方法。在制造晶体管的过程中，通过离子注入改变通道电荷载流子密度。测试晶体管形式的监测装置与制造晶体管同时在同一晶片上制造。在离子注入期间，测试晶体管的附录可以测量阈值电压和饱和电流。

2. 发明授权

US4394589A Logic circuit including at least one resistor or one transistor having a saturable resistor field effect transistor structure 失效
标题翻译：逻辑电路包括至少一个电阻器或一个具有可饱和电阻器场效应晶体管结构的晶体管
公开(公告)号：US4394589A
公开(公告)日：1983-07-19
申请号：US323535
申请日：1981-11-20
申请人： Ngu T. Pham , Gerard Nuzillat
发明人： Ngu T. Pham , Gerard Nuzillat
IPC分类号： H01L29/73 , H01L21/331 , H01L21/338 , H01L27/06 , H01L27/095 , H01L27/26 , H01L29/80 , H01L29/812 , H01L47/00 , H03K19/0952 , H03K19/094
CPC分类号： H03K19/0952 , H01L27/26 , H01L47/00
摘要： A logic circuit including an input stage, wherein a first field-effect transistor is in series with a first saturable resistor interposed on the drain side in the supply of the first transistor, and an output stage including a second transistor which is identical with the first and has a supply on the drain side which is common with the input stage supply. The gate of the second transistor is connected to the drain of the first transistor. The supply circuit of the second transistor is closed across a forward-biased diode, and a second saturable resistor on the ground of the common supply is connected to the source of the first transistor. At least a selected of the field effect transistors or the saturable resistors has a saturable resistor structure formed of a layer of semiconductor material on a semi-insulating substrate. The material is doped to set up a dipolar domain in respect of an electric field which is higher than a so-called critical value. The saturable resistor structure further includes a groove cut in the semiconductor layer between two ohmic contacts so as to define a residual channel in the material. The dimensions of the groove are such that the critical value of the electric field is overstepped in respect of a value of the order of one volt of the voltage between the ohmic contacts.
摘要翻译：一种包括输入级的逻辑电路，其中第一场效应晶体管与插在第一晶体管的电源中的漏极侧的第一可饱和电阻串联，以及包括与第一晶体管相同的第二晶体管的输出级并且在漏极侧具有与输入级电源相同的电源。第二晶体管的栅极连接到第一晶体管的漏极。第二晶体管的电源电路跨越正向偏置二极管闭合，并且公共电源的基极上的第二可饱和电阻器连接到第一晶体管的源极。至少选择的场效应晶体管或可饱和电阻器具有由半绝缘基板上的半导体材料层形成的可饱和电阻器结构。该材料被掺杂以在高于所谓的临界值的电场上建立偶极区域。可饱和电阻器结构还包括在两个欧姆接触之间的半导体层中切割的槽，以便在该材料中限定残余通道。凹槽的尺寸使得电场的临界值相对于欧姆接触之间的电压的一伏的值是超过的。

3. 发明授权

US4485316A Logic inverter, and a multi-output logic operator derived from this inverter, using at least two low-voltage-threshold field-effect transistors 失效
标题翻译：逻辑逆变器以及从该逆变器得到的多输出逻辑运算器，使用至少两个低电压阈值场效应晶体管
公开(公告)号：US4485316A
公开(公告)日：1984-11-27
申请号：US275623
申请日：1981-06-22
申请人： Gerard Nuzillat , Tung Pham Ngu , Georges Bert
发明人： Gerard Nuzillat , Tung Pham Ngu , Georges Bert
IPC分类号： H03K17/687 , H03K19/094 , H03K19/0952 , H03K19/017 , H03K19/20 , H03K19/21
CPC分类号： H03K19/09421 , H03K19/0952
摘要： A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom.One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.
摘要翻译：具有单个供电源的集成电路形式的高速逻辑逆变器使用“准正常”类型的场效应晶体管，逻辑运算器具有多个输入和多个输出。本发明的一个实施例从具有通过二极管输入的场效应晶体管栅极的反相器开始，并且其输出处于场效应晶体管的源极。通过在双栅极晶体管的栅极处提供输入（电源极和输入端子）与两对二极管之间的输入（通过将公共漏极连接的晶体管栅极连接到供电极与地面不同。

4. 发明授权

US4514649A High-entrance high-speed logic operator which has a complex digital function and utilizes at least one quasi-normally off MESFET 失效
标题翻译：具有复杂数字功能并使用至少一个准正常关闭MESFET的高入门高速逻辑运算器
公开(公告)号：US4514649A
公开(公告)日：1985-04-30
申请号：US265918
申请日：1981-05-21
申请人： Gerard Nuzillat , Georges Bert
发明人： Gerard Nuzillat , Georges Bert
IPC分类号： H03K19/094 , H03K19/0952 , H03K19/173 , H03K19/017 , H03K19/20
CPC分类号： H03K19/09421 , H03K19/0952
摘要： In the field of large-scale-integrated digital GaAs circuits, a high-entrance high-speed logical operator utilizing so-called "quasi-normally-off" Schottky-gate field-effect transistors (MESFETS) having a low threshold voltage. By means of a single very-high-speed logic gate, the operator thus performs AND - NAND - OR functions by utilizing in an input branch a saturable resistive load in series with a pair of quasi-normally-off MESFET's each having a maximum of two Schottky gates, the drains of the transistors being connected to an output transistor of the same type. Two identical portions of circuit are mounted in parallel with an output half-branch comprising a diode in series with another saturable resistive load.
摘要翻译：在大规模集成数字GaAs电路领域，利用具有低阈值电压的所谓的“准正常关断”肖特基半导体场效应晶体管（MESFETS）的高入口高速逻辑运算器。通过单个非常高速的逻辑门，操作者因此通过在输入分支中利用可饱和电阻负载与一对准正常关闭的MESFET串联执行“与非”或“ 两个肖特基门，晶体管的漏极连接到相同类型的输出晶体管。电路的两个相同的部分与包括与另一可饱和电阻负载串联的二极管的输出半支路并联安装。

5. 发明授权

US4402127A Method of manufacturing a logic circuit including at least one field-effect transistor structure of the normally-off type and at least one saturable resistor 失效
标题翻译：制造逻辑电路的方法，该逻辑电路包括至少一个常关型的场效晶体管结构和至少一个可饱和电阻
公开(公告)号：US4402127A
公开(公告)日：1983-09-06
申请号：US295108
申请日：1981-08-21
申请人： Ngu T. Pham , Gerard Nuzillat
发明人： Ngu T. Pham , Gerard Nuzillat
IPC分类号： H01L29/73 , H01L21/331 , H01L21/338 , H01L27/06 , H01L27/095 , H01L27/26 , H01L29/80 , H01L29/812 , H01L47/00 , H03K19/0952 , H01L21/302
CPC分类号： H03K19/0952 , H01L27/26 , H01L47/00
摘要： A method of manufacturing a logic circuit having at least one field effect transistor connected in series with at least one saturable resistor, wherein an active semiconductor layer is formed with a predetermined thickness on a semi-insulating substrate, ohmic contacts are deposited to produce source and drain regions for the resistor and the transistor, a Schottky contact is deposited between the resistor source and drain ohmic contacts to form a gate region which is then electrically connected to the resistor source contact by means of a metal connection, whereupon the localized thickness of the active layer is measured by measuring the drain-source current to the resistor upon application of a predetermined voltage thereto and a groove then cut between the source and drain contacts of the field effect transistor to obtain a predetermined channel depth from the bottom of the groove to the semi-insulating substrate. Then, a Schottky contact is deposited in the groove of the field effect transistor and the logic circuit completed conventionally.
摘要翻译：一种制造逻辑电路的方法，所述逻辑电路具有与至少一个可饱和电阻器串联连接的至少一个场效应晶体管，其中在半绝缘衬底上形成具有预定厚度的有源半导体层，沉积欧姆接触以产生源极和用于电阻器和晶体管的漏极区域，在电阻器源极和漏极欧姆触点之间沉积肖特基接触，以形成栅极区域，然后通过金属连接电连接到电阻器源极触点，于是，通过在施加预定电压时测量到电阻器的漏极 - 源极电流来测量有源层，然后在场效应晶体管的源极和漏极接触之间切割沟槽，以从槽的底部获得预定的沟道深度半绝缘基板。然后，在场效应晶体管的沟槽中沉积肖特基接触，并且常规地完成逻辑电路。

6. 发明授权

US4412336A Storage comparator, for regenerating digital electric signals and digital transmission system using such a comparator 失效
标题翻译：存储比较器，用于再生数字电信号和使用这种比较器的数字传输系统
公开(公告)号：US4412336A
公开(公告)日：1983-10-25
申请号：US203380
申请日：1980-11-03
申请人： Michel Peltier , Maurice Gloanec , Gerard Nuzillat , Vincent Maurel , Michel Charrier
发明人： Michel Peltier , Maurice Gloanec , Gerard Nuzillat , Vincent Maurel , Michel Charrier
IPC分类号： H04L25/03 , H03K5/08 , H03K17/30 , H03K17/687 , H03K19/0952 , H04L25/24 , H04L25/52 , H04L25/66 , H03K5/153
CPC分类号： H04L25/247
摘要： Device for regenerating digital signals transmitted along a coaxial line.So as to transmit information at flow rates greater than or equal to 650 Mbauds, the storage comparator of the invention is constructed in the form of an integrated circuit on AsGa and with negative threshold voltage MESFET transistors. It comprises an adjustable threshold voltage comparator stage, a type-D flip-flop for storage and resynchronization with respect to an external clock, and an output matching stage which may provide summation at its output.
摘要翻译：用于再生沿着同轴线传输的数字信号的装置。为了以大于或等于650M波特的流速传输信息，本发明的存储比较器以AsGa上的集成电路和负阈值电压MESFET晶体管的形式构成。它包括一个可调节的阈值电压比较器级，一个D型触发器，用于存储和重新同步相对于一个外部时钟;一个输出匹配级可以在其输出端提供求和。

7. 发明授权

US4277794A Structure for logic circuits 失效
标题翻译：逻辑电路结构
公开(公告)号：US4277794A
公开(公告)日：1981-07-07
申请号：US72841
申请日：1979-09-06
申请人： Gerard Nuzillat
发明人： Gerard Nuzillat
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082 , H03K19/082 , H03K19/091
CPC分类号： H01L27/0828 , H01L27/0237 , H03K19/082
摘要： A structure for logic circuits comprises a current source formed by a PNP transistor and two complementary transistors integrated on the same N-type substrate. A buried plate and P-type walls forms insulating housings. These two complementary transistors are of the vertical type and the PNP transistor has the buried layer as its collector. This buried layer and the insulating walls enable current to be injected into the PNPN structure which eliminates the need for surface interconnection networks and increases the integration density.
摘要翻译：逻辑电路的结构包括由PNP晶体管形成的电流源和集成在同一N型衬底上的两个互补晶体管。掩埋板和P型墙形成绝缘壳体。这两个互补晶体管是垂直型的，PNP晶体管具有埋层作为其集电极。该掩埋层和绝缘壁使电流能够注入到PNPN结构中，这消除了对表面互连网络的需要并增加了集成密度。

8. 发明授权

US4263340A Process for producing an integrated circuit 失效
标题翻译：集成电路的制造方法
公开(公告)号：US4263340A
公开(公告)日：1981-04-21
申请号：US17955
申请日：1979-03-06
申请人： Gerard Nuzillat , Christian Arnodo
发明人： Gerard Nuzillat , Christian Arnodo
IPC分类号： H01L21/338 , H01L21/768 , H01L27/06 , H01L29/20 , H01L29/812 , H01L29/48
CPC分类号： H01L29/20 , H01L21/768 , H01L21/76834 , H01L27/0605
摘要： An integrated circuit and process for producing an integrated circuit. The circuit includes two interconnection layers, a lower layer being separated from the substrate by a thin dielectric layer, and separated from the upper layer by a thick dielectric layer, the interconnections between the two interconnection layers being situated outside the zone of the active elements of the integrated circuit. The circuit comprises active elements deposited for example on portions of an n-type layer supported by a substrate of semi-insulating gallium arsenide. Ohmic and Schottky contacts are connected either to the lower interconnection layer or to the upper interconnection layer. The thin dielectric layer is for example a silica layer whose thickness is less than 1,000 Angstroms, the thick dielectric layer having a thickness of 5,000 to 10,000 Angstroms.
摘要翻译：一种用于制造集成电路的集成电路和工艺。电路包括两个互连层，下层通过薄的电介质层与衬底分离，并由上层由厚介电层分开，两个互连层之间的互连位于有源元件的区域之外集成电路。该电路包括例如沉积在由半绝缘砷化镓的衬底支撑的n型层的部分上的有源元件。欧姆和肖特基触点连接到下互连层或上互连层。薄介电层例如是厚度小于1000埃的二氧化硅层，厚介电层的厚度为5,000至10,000埃。

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