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1. 发明授权

US3955182A Transistorised memory cell and an integrated memory using such a cell 失效
标题翻译：晶体管存储单元和使用这种单元的集成存储器
公开(公告)号：US3955182A
公开(公告)日：1976-05-04
申请号：US560864
申请日：1975-03-21
申请人： Georges Bert
发明人： Georges Bert
IPC分类号： G11C11/412 , H03K3/356 , G11C11/40
CPC分类号： H03K3/356017 , G11C11/412
摘要： A memory cell as required for use in the building of integrated memories, which contains bistable trigger stages formed by two transistors, with a high operational reliability, a low power consumption and an access time of less than 0.01 microseconds for a store of 64 elements, is provided. To this end, low-consumption field-effect transistors are chosen, obtained by the ion implantation of an N-type channel, in order, in each cell, to form, in addition to the two transistors of the trigger stage, a pair of transistors connected as amplifier-followers. The selection of a cell is effected by raising the potential on the word line connected to the sources of the transistors of the trigger stage.
摘要翻译：用于构建集成存储器所需的存储器单元，其包含由两个晶体管形成的双稳态触发级，具有高操作可靠性，低功耗和对于64个元件的存储小于0.01微秒的访问时间，被提供。为此，通过在每个单元中依次离子注入N型沟道来选择低功耗场效应晶体管，除了触发级的两个晶体管之外还形成一对晶体管作为放大器跟随器连接。通过提高连接到触发级的晶体管的源极的字线上的电位来实现电池的选择。

2. 发明授权

US4514649A High-entrance high-speed logic operator which has a complex digital function and utilizes at least one quasi-normally off MESFET 失效
标题翻译：具有复杂数字功能并使用至少一个准正常关闭MESFET的高入门高速逻辑运算器
公开(公告)号：US4514649A
公开(公告)日：1985-04-30
申请号：US265918
申请日：1981-05-21
申请人： Gerard Nuzillat , Georges Bert
发明人： Gerard Nuzillat , Georges Bert
IPC分类号： H03K19/094 , H03K19/0952 , H03K19/173 , H03K19/017 , H03K19/20
CPC分类号： H03K19/09421 , H03K19/0952
摘要： In the field of large-scale-integrated digital GaAs circuits, a high-entrance high-speed logical operator utilizing so-called "quasi-normally-off" Schottky-gate field-effect transistors (MESFETS) having a low threshold voltage. By means of a single very-high-speed logic gate, the operator thus performs AND - NAND - OR functions by utilizing in an input branch a saturable resistive load in series with a pair of quasi-normally-off MESFET's each having a maximum of two Schottky gates, the drains of the transistors being connected to an output transistor of the same type. Two identical portions of circuit are mounted in parallel with an output half-branch comprising a diode in series with another saturable resistive load.
摘要翻译：在大规模集成数字GaAs电路领域，利用具有低阈值电压的所谓的“准正常关断”肖特基半导体场效应晶体管（MESFETS）的高入口高速逻辑运算器。通过单个非常高速的逻辑门，操作者因此通过在输入分支中利用可饱和电阻负载与一对准正常关闭的MESFET串联执行“与非”或“ 两个肖特基门，晶体管的漏极连接到相同类型的输出晶体管。电路的两个相同的部分与包括与另一可饱和电阻负载串联的二极管的输出半支路并联安装。

3. 发明授权

US4434379A Inverter using low-threshold-voltage field-effect transistors and a switching diode, formed as an integrated circuit 失效
标题翻译：逆变器采用低阈值电压场效应晶体管和开关二极管，形成集成电路
公开(公告)号：US4434379A
公开(公告)日：1984-02-28
申请号：US244873
申请日：1981-03-18
申请人： Georges Bert
发明人： Georges Bert
IPC分类号： H01L29/78 , H03K17/687 , H03K17/74 , H03K19/08 , H03K19/0952 , H03K19/003 , H03K19/094 , H03K19/20
CPC分类号： H03K19/0952
摘要： A logic inverter using field-effect transistors of the "normally off" or "quasi normally off" type with relatively wide tolerance on the threshold voltage. It comprises a first half-stage comprising a field-effect transistor with low threshold voltage, whose source, instead of being connected to ground, is connected to the gate of a second transistor placed in a second half-stage in series with a diode which plays an essential role in the switching of the inverter.
摘要翻译：逻辑逆变器采用具有相对较宽的阈值电压公差的“常态”或“准正常关断”型场效应晶体管。它包括具有低阈值电压的场效应晶体管的第一半级，其源极而不是连接到地，连接到与二极管串联的第二半晶体中的第二晶体管的栅极，二极管在逆变器的切换中起着至关重要的作用。

4. 发明授权

US4485316A Logic inverter, and a multi-output logic operator derived from this inverter, using at least two low-voltage-threshold field-effect transistors 失效
标题翻译：逻辑逆变器以及从该逆变器得到的多输出逻辑运算器，使用至少两个低电压阈值场效应晶体管
公开(公告)号：US4485316A
公开(公告)日：1984-11-27
申请号：US275623
申请日：1981-06-22
申请人： Gerard Nuzillat , Tung Pham Ngu , Georges Bert
发明人： Gerard Nuzillat , Tung Pham Ngu , Georges Bert
IPC分类号： H03K17/687 , H03K19/094 , H03K19/0952 , H03K19/017 , H03K19/20 , H03K19/21
CPC分类号： H03K19/09421 , H03K19/0952
摘要： A high-speed logic inverter, in the form of an integrated circuit, with a single supply source, using field-effect transistors of the "quasi-normally-off" type, and the logic operators having several inputs and several outputs which derive therefrom.One embodiment of the invention starts from an inverter with input, through a diode, on a field-effect transistor gate, and with its output at the source of a field-effect transistor. This basic diagram is added to by providing the input (between supply pole and input terminal) with two pairs of diodes ending at the gates of a dual-gate transistor, and by providing independent outputs obtained by connecting the common drain connected transistor gates to the supply pole distinct from ground.
摘要翻译：具有单个供电源的集成电路形式的高速逻辑逆变器使用“准正常”类型的场效应晶体管，逻辑运算器具有多个输入和多个输出。本发明的一个实施例从具有通过二极管输入的场效应晶体管栅极的反相器开始，并且其输出处于场效应晶体管的源极。通过在双栅极晶体管的栅极处提供输入（电源极和输入端子）与两对二极管之间的输入（通过将公共漏极连接的晶体管栅极连接到供电极与地面不同。

5. 发明授权

US4568843A Bistable logic device, operating from DC to 10 GHz, and frequency divider including this bistable device 失效
标题翻译：双稳态逻辑器件，工作在直流到10 GHz，分频器包括双稳态器件
公开(公告)号：US4568843A
公开(公告)日：1986-02-04
申请号：US505175
申请日：1983-06-17
申请人： Maurice Gloanec , Georges Bert , Ernesto Perea
发明人： Maurice Gloanec , Georges Bert , Ernesto Perea
IPC分类号： H03K3/037 , H03K3/356 , H03K3/289 , H03K3/288
CPC分类号： H03K3/037 , H03K3/356069
摘要： A bistable logic device, of the RSTT type, operating up to X band. The bistable logic device is organized into three stages: an input stage of four NOR operators (21, 31, 41, 51), a second stage of two OR operators (61, 71) and an output stage of two OR operators (62, 72). Each NOR operator of the input stage drives in parallel an OR operator of the second stage and an OR operator of the output stage. Each of the four OR operators are fed back to an input of one of the four NOR operators of the input stage. The organization in logic NOR/OR form makes it possible to use faster single gate transistors. The present invention may be particularly useful to frequency dividers for interfacing between signals at GHz frequency and measurement and control circuits at MHz frequency.
摘要翻译： RST和upbar＆T类型的双稳态逻辑器件，可运行到X频段。双稳态逻辑器件分为三个阶段：四个NOR运算符（21,31,41,51）的输入级，两个OR运算符（61,71）的第二级和两个OR运算符的输出级（62， 72）。输入级的每个NOR运算符并行驱动第二级的OR运算符和输出级的OR运算符。四个OR运算符中的每一个被反馈到输入级的四个NOR运算符之一的输入。逻辑NOR / OR形式的组织使得可以使用更快的单栅极晶体管。本发明对于用于在GHz频率的信号与MHz频率的测量和控制电路之间进行接口的分频器可能是特别有用的。

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