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1. 发明授权

US06411334B1 Aspect ratio correction using digital filtering 有权
标题翻译：使用数字滤波的宽高比校正
公开(公告)号：US06411334B1
公开(公告)日：2002-06-25
申请号：US09264140
申请日：1999-03-05
申请人： Gerard K. Yeh , Anoush Khazeni , David Auld , Bruce K. Holmer , Meng-Day Yu
发明人： Gerard K. Yeh , Anoush Khazeni , David Auld , Bruce K. Holmer , Meng-Day Yu
IPC分类号： H04N1120
CPC分类号： H04N7/0122 , G06F3/14 , G06T3/40 , G09G5/363 , G09G5/391 , G09G5/395 , G09G2320/0247 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G2360/123 , H04N5/14 , H04N5/21 , H04N9/641
摘要： The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.
摘要翻译：本发明是一种用于通过将像素数据的目标数组的比例因子缩放存储器中的像素数据的源阵列来校正显示器的纵横比的方法和装置。该装置包括系数单元，寄存器单元和运算单元。系数单元耦合到缓冲器以加载N个系数。寄存器单元耦合到源阵列以与系数单元同步地加载N个像素数据。 N像素数据根据比例因子在源阵列的位置开始。算术单元耦合到系数单元和寄存器单元，以使用相应的N个系数对所加载的N个像素数据执行滤波操作。算术单元产生对应于目的地阵列中的缩放像素的滤波输出。

2. 发明授权

US06327000B1 Efficient image scaling for scan rate conversion 有权
标题翻译：扫描速率转换的高效图像缩放
公开(公告)号：US06327000B1
公开(公告)日：2001-12-04
申请号：US09285491
申请日：1999-04-02
申请人： David Auld , Gerard K. Yeh , Peter Trajmar , C. Dardy Chang , Meng-Day Yu
发明人： David Auld , Gerard K. Yeh , Peter Trajmar , C. Dardy Chang , Meng-Day Yu
IPC分类号： H04N701
CPC分类号： H04N5/14 , G06T3/4007 , G06T2200/28 , H04N7/01 , H04N7/012
摘要： The present invention is a method and apparatus for converting scan rates of image data in a memory. A buffer stores a source image data. A scaling filter is coupled to the buffer to scale the source image data.
摘要翻译：本发明是用于转换存储器中的图像数据的扫描速率的方法和装置。缓冲器存储源图像数据。缩放滤波器耦合到缓冲器以缩放源图像数据。

3. 发明授权

US06563511B1 Anti-flickering for video display based on pixel luminance 有权
标题翻译：基于像素亮度的视频显示防闪烁
公开(公告)号：US06563511B1
公开(公告)日：2003-05-13
申请号：US09263121
申请日：1999-03-05
申请人： Gerard K. Yeh , Anoush Khazeni
发明人： Gerard K. Yeh , Anoush Khazeni
IPC分类号： G09G500
CPC分类号： H04N7/0122 , G09G5/36 , G09G2320/0247 , H04N5/21 , H04N5/4401 , H04N5/46 , H04N7/0132 , H04N9/641
摘要： The present invention is a method and apparatus to generate an anti-flickered pixel from a source pixel having a source pixel value in a display memory. The apparatus comprises a plurality of storage elements, a filter, a comparator, and an output selector. The plurality of storage elements store a sequence of pixels in the display memory which includes the source pixel. The filter is coupled to the plurality of storage elements to filter the sequence of pixels. The filter generates a filtered pixel corresponding to the source pixel. The comparator is coupled to the plurality of storage elements to compare the source pixel value with a threshold value. The comparator generates a comparison result. The output selector is coupled to the filter and the storage elements to select one of the source and filtered pixels according to the comparison result. The selected one of the source and filtered pixels is the anti-flickered pixel.
摘要翻译：本发明是一种从显示存储器中具有源像素值的源像素生成防闪烁像素的方法和装置。该装置包括多个存储元件，滤波器，比较器和输出选择器。多个存储元件将包括源像素的一系列像素存储在显示存储器中。滤波器耦合到多个存储元件以对像素序列进行滤波。滤波器生成对应于源像素的滤波像素。比较器耦合到多个存储元件，以将源像素值与阈值进行比较。比较器产生比较结果。根据比较结果，输出选择器耦合到滤波器和存储元件以选择源和滤波像素之一。所选择的源和滤波像素之一是反闪烁像素。

4. 发明授权

US07986326B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US07986326B1
公开(公告)日：2011-07-26
申请号：US12701433
申请日：2010-02-05
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G09G5/39
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

5. 发明授权

US07688324B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US07688324B1
公开(公告)日：2010-03-30
申请号：US10288402
申请日：2002-11-04
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G09G5/39
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

6. 发明授权

US08902241B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US08902241B1
公开(公告)日：2014-12-02
申请号：US13174456
申请日：2011-06-30
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G06F15/00 , G06T1/60 , G06F13/18 , H04N7/173
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

7. 发明授权

US06526583B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US06526583B1
公开(公告)日：2003-02-25
申请号：US09263454
申请日：1999-03-05
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： H04N7173
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

8. 发明授权

US06353459B1 Method and apparatus for down conversion of video data 有权
标题翻译：用于视频数据下转换的方法和装置
公开(公告)号：US06353459B1
公开(公告)日：2002-03-05
申请号：US09283823
申请日：1999-03-31
申请人： Gerard K. Yeh , Hsiang O-Yang , David Auld
发明人： Gerard K. Yeh , Hsiang O-Yang , David Auld
IPC分类号： H04N701
CPC分类号： H04N7/0105 , H04N7/0125
摘要： The invention provides a method and apparatus for conversion of video data from a source format to a second destination. Conversion can be performed in real time and intermediate data is stored in a buffer. Converted video data is written into the buffer at a first rate and read out of the buffer at a second rate. In order to avoid overflow and underflow conditions, a threshold value is determined based, at least in part, on the video format being converted. The threshold value indicates a point in frame conversion at which converted data is read out of the buffer.
摘要翻译：本发明提供一种用于将视频数据从源格式转换为第二目的地的方法和装置。转换可以实时执行，中间数据存储在缓冲区中。转换的视频数据以第一速率写入缓冲器，并以第二速率读出缓冲器。为了避免溢出和下溢条件，至少部分地基于要转换的视频格式来确定阈值。阈值表示从缓冲器读出转换数据的帧转换点。

9. 发明授权

US06556193B1 De-interlacing video images using patch-based processing 有权
标题翻译：使用基于补丁的处理去隔行视频图像
公开(公告)号：US06556193B1
公开(公告)日：2003-04-29
申请号：US09285486
申请日：1999-04-02
申请人： David Auld , Gerard K. Yeh , Peter Trajmar
发明人： David Auld , Gerard K. Yeh , Peter Trajmar
IPC分类号： G06T100
CPC分类号： G09G5/14 , G06T3/4007 , G09G2310/0229 , G09G2340/02 , G09G2340/0414 , G09G2340/0421 , G09G2340/125 , H04N7/01 , H04N7/012 , H04N7/0135
摘要： The present invention is a method and apparatus for de-interlacing image data in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A de-interlacing circuit is coupled to the read interface circuit to de-interlace the image data in the patch from the buffer. A receive circuit is coupled to the de-interlacing circuit to re-organize the de-interlaced image data.
摘要翻译：本发明是用于将存储器中的图像数据去隔行的方法和装置。读接口电路耦合到存储器以将图像数据的片段从存储器传送到缓冲器。去隔行电路耦合到读接口电路，以从缓冲器中去除隔行扫描图像数据。接收电路耦合到去隔行电路以重新组织去隔行图像数据。

10. 发明授权

US06411333B1 Format conversion using patch-based filtering 有权
标题翻译：使用基于补丁的过滤格式转换
公开(公告)号：US06411333B1
公开(公告)日：2002-06-25
申请号：US09285490
申请日：1999-04-02
申请人： David Auld , Gerard K. Yeh , Peter Trajmar , C. Dardy Chang , Kevin P. Acken
发明人： David Auld , Gerard K. Yeh , Peter Trajmar , C. Dardy Chang , Kevin P. Acken
IPC分类号： H04N701
CPC分类号： G06T3/40 , G09G5/14 , G09G5/393 , G09G2310/0229 , G09G2340/02 , G09G2340/0414 , G09G2340/0421 , G09G2340/125 , G09G2360/02 , H04N5/4401 , H04N5/45 , H04N5/46 , H04N7/012 , H04N7/0135 , H04N7/0137 , H04N9/642 , H04N21/4316 , H04N21/440218 , H04N21/440263 , H04N21/4435
摘要： The invention is a method and apparatus for processing image data stored in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A scale filter is coupled to the read interface circuit to scale the image data in the patch from the buffer. A receive circuit is coupled to the scale filter to re-organize the scaled image data.
摘要翻译：本发明是用于处理存储在存储器中的图像数据的方法和装置。读接口电路耦合到存储器以将图像数据的片段从存储器传送到缓冲器。比例滤波器耦合到读接口电路以从缓冲器缩放补丁中的图像数据。接收电路耦合到缩放滤波器以重新组织缩放的图像数据。

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