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1. 发明授权

US07986326B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US07986326B1
公开(公告)日：2011-07-26
申请号：US12701433
申请日：2010-02-05
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G09G5/39
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

2. 发明授权

US07688324B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US07688324B1
公开(公告)日：2010-03-30
申请号：US10288402
申请日：2002-11-04
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G09G5/39
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

3. 发明授权

US06466220B1 Graphics engine architecture 有权
标题翻译：图形引擎架构
公开(公告)号：US06466220B1
公开(公告)日：2002-10-15
申请号：US09263161
申请日：1999-03-05
申请人： Joseph F. Cesana , Peter Trajmar , Edward Wang , Hank Guo , Steve Chiou , Bruce K. Holmer , David Auld
发明人： Joseph F. Cesana , Peter Trajmar , Edward Wang , Hank Guo , Steve Chiou , Bruce K. Holmer , David Auld
IPC分类号： G06F1300
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/0407 , G09G2340/10
摘要： A method and apparatus for display of graphical data is described. The invention provides an architecture for graphics processing. The architecture includes pipelined processing and support for multi-regional graphics. In one embodiment, a graphics driver according to the invention can receive multiple independent streams of graphical data that can be in different graphical formats. The independent streams are synchronized and converted to a common format prior to being processed. In one embodiment, multi-regional graphics are supported with off-screen and on-screen memory regions for processing. The regions of the multi-regional graphic are rendered in an off-screen memory. The data in the off-screen memory are converted to a common format and copied to on-screen memory. The data in the on-screen memory is used to generate an output image. Alpha blending can also be programmed to provide multi-regional graphics or other graphical features. In one embodiment, graphics processing is programmable and can be paced using a set of registers.
摘要翻译：描述了用于显示图形数据的方法和装置。本发明提供了用于图形处理的架构。该架构包括流水线处理和支持多区域图形。在一个实施例中，根据本发明的图形驱动器可以接收可以处于不同图形格式的多个独立的图形数据流。在处理之前，独立流被同步并转换为通用格式。在一个实施例中，多区域图形由用于处理的离屏和屏幕上存储器区域来支持。多区域图形的区域呈现在离屏存储器中。离屏存储器中的数据被转换为通用格式并复制到屏幕存储器。屏幕存储器中的数据用于生成输出图像。 Alpha混合也可以编程为提供多区域图形或其他图形特征。在一个实施例中，图形处理是可编程的，并且可以使用一组寄存器进行调整。

4. 发明授权

US06411334B1 Aspect ratio correction using digital filtering 有权
标题翻译：使用数字滤波的宽高比校正
公开(公告)号：US06411334B1
公开(公告)日：2002-06-25
申请号：US09264140
申请日：1999-03-05
申请人： Gerard K. Yeh , Anoush Khazeni , David Auld , Bruce K. Holmer , Meng-Day Yu
发明人： Gerard K. Yeh , Anoush Khazeni , David Auld , Bruce K. Holmer , Meng-Day Yu
IPC分类号： H04N1120
CPC分类号： H04N7/0122 , G06F3/14 , G06T3/40 , G09G5/363 , G09G5/391 , G09G5/395 , G09G2320/0247 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G2360/123 , H04N5/14 , H04N5/21 , H04N9/641
摘要： The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.
摘要翻译：本发明是一种用于通过将像素数据的目标数组的比例因子缩放存储器中的像素数据的源阵列来校正显示器的纵横比的方法和装置。该装置包括系数单元，寄存器单元和运算单元。系数单元耦合到缓冲器以加载N个系数。寄存器单元耦合到源阵列以与系数单元同步地加载N个像素数据。 N像素数据根据比例因子在源阵列的位置开始。算术单元耦合到系数单元和寄存器单元，以使用相应的N个系数对所加载的N个像素数据执行滤波操作。算术单元产生对应于目的地阵列中的缩放像素的滤波输出。

5. 发明授权

US08902241B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US08902241B1
公开(公告)日：2014-12-02
申请号：US13174456
申请日：2011-06-30
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： G06F15/00 , G06T1/60 , G06F13/18 , H04N7/173
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

6. 发明授权

US07710424B1 Method and system for a texture-aware virtual memory subsystem 有权
标题翻译：纹理感知虚拟内存子系统的方法和系统
公开(公告)号：US07710424B1
公开(公告)日：2010-05-04
申请号：US10993679
申请日：2004-11-18
申请人： Edward A. Hutchins , James T. Battle , Bruce K. Holmer
发明人： Edward A. Hutchins , James T. Battle , Bruce K. Holmer
IPC分类号： G06F13/00 , G06T11/40 , G09G5/36 , G09G5/00
CPC分类号： G09G5/391 , G09G5/363 , G09G5/393 , G09G5/395
摘要： A method and system for accessing texture data is disclosed. The method includes the step of storing a low resolution version of a block of texture data in a low latency memory and storing a high resolution version of the block of texture data in high latency memory. Upon a request for the high resolution version of the block of texture data, the high resolution version is fetched from the high latency memory to the low latency memory. The low resolution version is subsequently accessed from the low latency memory until the high resolution version is fetched into the low latency memory.
摘要翻译：公开了一种访问纹理数据的方法和系统。该方法包括将低分辨率版本的纹理数据块存储在低延迟存储器中并将高分辨率版本的纹理数据块存储在高延迟存储器中的步骤。在要求纹理数据块的高分辨率版本的情况下，将高分辨率版本从高延迟存储器提取到低延迟存储器。低分辨率版本随后从低延迟存储器访问，直到高分辨率版本被提取到低延迟存储器中。

7. 发明授权

US06526583B1 Interactive set-top box having a unified memory architecture 有权
标题翻译：互动机顶盒具有统一的内存架构
公开(公告)号：US06526583B1
公开(公告)日：2003-02-25
申请号：US09263454
申请日：1999-03-05
申请人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
发明人： David R. Auld , Bruce K. Holmer , Hong-Jyeh Jason Huang , Gerard K. Yeh
IPC分类号： H04N7173
CPC分类号： H04N21/426 , G06T15/005 , H04N7/17318 , H04N21/42653 , H04N21/42692 , H04N21/4435 , H04N21/4622 , H04N21/4782
摘要： According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.
摘要翻译：根据一个实施例，图形/视频处理器包括存储器控制器。存储器控制器包括：第一仲裁器，其接收存储器客户机访问存储器设备的请求;以及耦合到第一仲裁器的第一存储器缓冲器。第一个仲裁器存储由第一仲裁器选择的客户机请求。存储器控制器还包括耦合到第一存储器缓冲器的第二仲裁器和耦合到第二仲裁器的第二存储器缓冲器。第二仲裁器从存储在第一存储器缓冲器中的存储器客户端请求接收请求。第二存储器缓冲器存储由第二仲裁器选择的客户机请求。此外，存储器控制器包括耦合到第二存储器缓冲器的第三仲裁器。第三仲裁器提供存储器设备对存储在第二存储器缓冲器中的客户端请求的访问。

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