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1. 发明授权

US06739048B2 Process of fabricating a circuitized structure 失效
标题翻译：制造电路化结构的工艺
公开(公告)号：US06739048B2
公开(公告)日：2004-05-25
申请号：US09491755
申请日：2000-01-27
申请人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
发明人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
IPC分类号： H01K310
CPC分类号： H05K3/388 , H01L21/4846 , H01L21/4857 , H05K3/0023 , H05K3/16 , H05K3/4602 , H05K2201/09536 , H05K2201/096 , H05K2203/1581 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
摘要翻译：提供了一种制造电路化结构的工艺。该方法包括提供其上具有电路的有机基底的步骤; 在有机基板上施加电介质膜; 在电介质膜中形成微孔; 在电介质膜和微孔上溅射金属种子层; 在金属籽晶层上镀金属层; 并在其上形成电路图案。

2. 发明授权

US6131279A Integrated manufacturing packaging process 失效
标题翻译：集成制造包装过程
公开(公告)号：US6131279A
公开(公告)日：2000-10-17
申请号：US5182
申请日：1998-01-08
申请人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
发明人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , William John Rudik , James Warren Wilson , William Earl Wilson
IPC分类号： H01L21/48 , H05K3/00 , H05K3/16 , H05K3/38 , H05K3/46 , H01K3/10
CPC分类号： H05K3/388 , H01L21/4846 , H01L21/4857 , H05K3/4602 , H05K2201/09536 , H05K2201/096 , H05K2203/1581 , H05K3/0023 , H05K3/16 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.
摘要翻译：提供一种制造电路化基板的工艺，其包括以下步骤：提供其上具有电路的有机基板; 在有机基板上施加电介质膜; 在所述介电膜中形成微孔; 在电介质膜上和所述微孔中溅射金属种子层; 在金属籽晶层上镀金属层; 并在其上形成电路图案。

3. 发明授权

US6027858A Process for tenting PTH's with PID dry film 失效
标题翻译：使用PID干膜遮盖PTH的过程
公开(公告)号：US6027858A
公开(公告)日：2000-02-22
申请号：US870950
申请日：1997-06-06
申请人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , Heinke Marcello , James Warren Wilson , William Earl Wilson
发明人： Gerald Walter Jones , Ross William Keesler , Voya Rista Markovich , Heinke Marcello , James Warren Wilson , William Earl Wilson
IPC分类号： G03F7/038 , G03F7/16 , H05K3/00 , H05K3/46 , G03C11/12 , G03F7/00
CPC分类号： H05K3/0094 , G03F7/0385 , G03F7/161 , H05K3/4602 , H05K2201/09536 , H05K2203/066 , H05K2203/1394 , H05K3/0023
摘要： A process of tenting plated through holes with a photoimageable dielectric is provided which includes a dielectric film comprising a photoimageable epoxy based resin layer and a peelable polyester layer. In accordance with the process of the present invention, the peelable polyester layer of the dielectric film is removed prior to baking, developing, patterning or curing the structure.
摘要翻译：提供了一种用可光成像的电介质通孔穿孔的方法，其包括包括可光成像的环氧树脂层和可剥离聚酯层的电介质膜。根据本发明的方法，在烘烤，显影，图案化或固化该结构之前去除电介质膜的可剥离聚酯层。

4. 发明授权

US5981880A Electronic device packages having glass free non conductive layers 失效
标题翻译：具有无玻璃的非导电层的电子器件封装
公开(公告)号：US5981880A
公开(公告)日：1999-11-09
申请号：US699902
申请日：1996-08-20
申请人： Bernd Karl-Heinz Appelt , Anilkumar Chinuprasad Bhatt , James W. Fuller, Jr. , John Matthew Lauffer , Voya Rista Markovich , William John Rudik , William Earl Wilson
发明人： Bernd Karl-Heinz Appelt , Anilkumar Chinuprasad Bhatt , James W. Fuller, Jr. , John Matthew Lauffer , Voya Rista Markovich , William John Rudik , William Earl Wilson
IPC分类号： H01L21/48 , H01L23/00 , H01L23/498 , H05K1/03 , H05K3/42 , H05K3/46 , H05K1/00
CPC分类号： H01L23/564 , H01L21/481 , H01L23/498 , H01L23/49894 , H05K3/429 , H05K3/4626 , H05K3/4641 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/036 , H05K1/0366 , H05K2201/0195 , H05K2201/0769 , H05K2201/09718 , H05K2201/09881
摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
摘要翻译：用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板包括用于分离和绝缘电源芯的无玻璃电介质，电路或电镀通孔，以防止由导电材料沿着玻璃基预浸料衬底的迁移。

5. 发明授权

US5922517A Method of preparing a substrate surface for conformal plating 失效
标题翻译：制备用于保形电镀的基板表面的方法
公开(公告)号：US5922517A
公开(公告)日：1999-07-13
申请号：US662165
申请日：1996-06-12
申请人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
发明人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
IPC分类号： H05K3/00 , G03F7/095 , H05K3/18 , G03F7/00
CPC分类号： H05K3/184 , G03F7/095
摘要： Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.
摘要翻译：通过避免催化种子材料沉积到衬底的非电路区域上，防止了在保形电镀过程中导电电路特征之间的桥接。准备通过完全添加的方法在非导电基材上形成电路特征，外来种子材料被捕获在两层可光成像膜之间，由此在电镀期间不可用，或者沉积在水性可光成像膜的表面上，在电镀之前移除。实施本发明的方法消除了在初始镀覆之后以及在初始镀覆之前对贵金属进行适形电镀之前的种子去除的需要。

6. 发明授权

US5905018A Method of preparing a substrate surface for conformal plating 失效
公开(公告)号：US5905018A
公开(公告)日：1999-05-18
申请号：US957275
申请日：1997-10-24
申请人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
发明人： Anilkumar Chinuprasad Bhatt , Ashwinkumar C. Bhatt , Voya Rista Markovich , William Earl Wilson , Gerald Walter Jones
IPC分类号： H05K3/00 , G03F7/095 , H05K3/18 , G03F7/20
CPC分类号： H05K3/184 , G03F7/095
摘要： Bridging between electrically conductive circuit features during conformal plating is prevented by avoiding the deposition of catalytic seed material onto non-circuit areas of the substrate. Preparatory to forming electrical circuit features on a nonconductive substrate by the full additive process, extraneous seed material is either trapped between two layers of a photoimageable film, whereby it is unavailable during plating, or deposited on the surface of an aqueous photoimageable film, which is removed prior to plating. The method embodying the present invention eliminates the need for seed removal after initial plating and prior to conformal plating of a precious metal over the initial plating.

7. 发明授权

US5997997A Method for reducing seed deposition in electroless plating 失效
标题翻译：减少化学镀中种子沉积的方法
公开(公告)号：US5997997A
公开(公告)日：1999-12-07
申请号：US874641
申请日：1997-06-13
申请人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
发明人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
IPC分类号： C23C18/16 , H05K3/18 , H05K3/38 , B32B9/00 , B05D3/00
CPC分类号： C23C18/2033 , C23C18/1605 , C23C18/2086 , C23C18/285 , C23C18/30 , H05K3/387 , H05K2203/1105 , H05K2203/122 , H05K3/181 , H05K3/381 , H05K3/389 , Y10S428/901 , Y10T428/24917 , Y10T428/31522
摘要： The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.
摘要翻译：本发明提供了减少沉积在聚合物电介质表面上的种子的量的新方法。该方法包括以下步骤：提供涂覆有聚合物介电层的工件; 烘烤工件以改变聚合物介电层的表面; 然后将种子施加到聚合物介电层上，并将金属无电镀在种子层上。本发明还涉及通过本发明的方法制造的电路板。

8. 发明授权

US06680440B1 Circuitized structures produced by the methods of electroless plating 失效
标题翻译：通过无电镀方法生产的电路结构
公开(公告)号：US06680440B1
公开(公告)日：2004-01-20
申请号：US09027856
申请日：1998-02-23
申请人： David John Russell , Gerald Walter Jones , Heike Marcello , Voya Rista Markovich
发明人： David John Russell , Gerald Walter Jones , Heike Marcello , Voya Rista Markovich
IPC分类号： H05K116
CPC分类号： H05K3/287 , G03F7/0385 , H05K3/0023 , H05K3/184 , H05K3/243 , H05K2203/072
摘要： The present invention provides new methods for electroless plating of metal particularly gold and copper onto substrates, such as circuitized substrates, which reduces processing steps, reduces metal consumption, and reduces the scraping of parts due to contamination. The method employs a permanent plating resist. The method for electrolessly plating metal onto a substrate, including the following steps: providing: an uncured, photoimagable, dielectric permanent plating resist comprising: from about 10 to 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to 130,000; from about 20 to 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to 10,000; from 0 to 50% of a diglycidyl ether of bisphenol A having a molecular weight of from about 600 to 2,500; and from about 0.1 to 15 parts by weight of the total resin weight, a cationic photoinitiator; applying the permanent plating resist on the substrate; photopatterning the permanent plating resist to form apertures therein which expose areas of the substrate; and electrolessly plating metal onto the exposed areas of the substrate. The permanent plating resist is useful to protect the substrate areas including for example metallized features on the substrate, from the electroless deposition of metal during electroless plating; thus selective plating of metal is achieved. The permanent plating resist is not degraded by conventional gold or copper electroless baths. The invention also relates to circuitized structures produced by the methods of electroless plating.
摘要翻译：本发明提供了金属特别是金和铜在电路化基板等基板上进行化学镀的新方法，其减少了加工步骤，降低了金属消耗，并减少了由于污染引起的部件刮擦。该方法采用永久电镀抗蚀剂。将金属无电镀在基板上的方法，包括以下步骤：提供：未固化的，可光成像的绝缘永久电镀抗蚀剂，其包含：约10至80％的作为表氯醇和双酚A的缩合产物的苯氧基多元醇树脂，其具有分子量为约40,000至130,000; 约20至90％的分子量为约4,000至10,000的环氧化多官能双酚A甲醛酚醛清漆树脂; 0至50％的分子量为约600至2,500的双酚A的二缩水甘油醚; 和约0.1至15重量份的总树脂重量，阳离子光引发剂; 在基板上施加永久电镀抗蚀剂; 对永久电镀抗蚀剂进行光图案化以在其中形成露出基板的区域的孔; 并将金属化学镀在衬底的暴露区域上。永久电镀抗蚀剂可用于保护衬底区域，包括例如基板上的金属化特征，在化学镀期间的金属化学沉积; 从而实现了金属的选择性镀覆。永久电镀抗蚀剂不会被常规的金或铜无电镀浴降解。本发明还涉及通过化学镀方法制造的电路结构。

9. 发明授权

US5935652A Method for reducing seed deposition in electroless plating 失效
公开(公告)号：US5935652A
公开(公告)日：1999-08-10
申请号：US46245
申请日：1998-03-23
申请人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
发明人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
IPC分类号： C23C18/16 , H05K3/18 , H05K3/38 , B05D3/02
CPC分类号： C23C18/2033 , C23C18/1605 , C23C18/2086 , C23C18/285 , C23C18/30 , H05K3/387 , H05K2203/1105 , H05K2203/122 , H05K3/181 , H05K3/381 , H05K3/389 , Y10S428/901 , Y10T428/24917 , Y10T428/31522
摘要： The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.

10. 发明授权

US06547974B1 Method of producing fine-line circuit boards using chemical polishing 失效
标题翻译：使用化学抛光生产细线电路板的方法
公开(公告)号：US06547974B1
公开(公告)日：2003-04-15
申请号：US08495277
申请日：1995-06-27
申请人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
发明人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
IPC分类号： H01B1300
CPC分类号： H05K3/22 , H05K3/06 , H05K3/062 , H05K3/108 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/0392 , H05K2203/1476
摘要： A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.
摘要翻译：通过根据限定所需电路路径的电路掩模图案化抗蚀剂层来制造印刷电路板。抗蚀剂图案层通过在所需的电路路径中从基板上去除抗蚀剂而形成，并且导电材料被电镀在由电路掩模限定的抗蚀剂空隙中的基板上，使得导电材料相对于基板的高度等于或等于超过抗蚀剂层相对于基底的高度。将低反应性溶液施加在导电材料上并除去导电材料的表面部分。当溶液去除导电层时，其形成膜阻挡层并且溶液组成发生变化，这两者基本上禁止任何进一步去除导电材料。接下来，从板上去除膜屏障，允许另一个膜屏障形成刺激去除另外的导电材料。重复去除步骤，直到导电材料相对于抗蚀剂层的高度处于期望的高度。然后使用常规电路板制造技术完成电路板。

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