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1. 发明授权

US5997997A Method for reducing seed deposition in electroless plating 失效
标题翻译：减少化学镀中种子沉积的方法
公开(公告)号：US5997997A
公开(公告)日：1999-12-07
申请号：US874641
申请日：1997-06-13
申请人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
发明人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
IPC分类号： C23C18/16 , H05K3/18 , H05K3/38 , B32B9/00 , B05D3/00
CPC分类号： C23C18/2033 , C23C18/1605 , C23C18/2086 , C23C18/285 , C23C18/30 , H05K3/387 , H05K2203/1105 , H05K2203/122 , H05K3/181 , H05K3/381 , H05K3/389 , Y10S428/901 , Y10T428/24917 , Y10T428/31522
摘要： The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.
摘要翻译：本发明提供了减少沉积在聚合物电介质表面上的种子的量的新方法。该方法包括以下步骤：提供涂覆有聚合物介电层的工件; 烘烤工件以改变聚合物介电层的表面; 然后将种子施加到聚合物介电层上，并将金属无电镀在种子层上。本发明还涉及通过本发明的方法制造的电路板。

2. 发明授权

US5935652A Method for reducing seed deposition in electroless plating 失效
公开(公告)号：US5935652A
公开(公告)日：1999-08-10
申请号：US46245
申请日：1998-03-23
申请人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
发明人： Anastasios Peter Angelopoulos , Gerald Walter Jones , Luis Jesus Matienzo , Thomas Richard Miller , Voya Rista Markovich
IPC分类号： C23C18/16 , H05K3/18 , H05K3/38 , B05D3/02
CPC分类号： C23C18/2033 , C23C18/1605 , C23C18/2086 , C23C18/285 , C23C18/30 , H05K3/387 , H05K2203/1105 , H05K2203/122 , H05K3/181 , H05K3/381 , H05K3/389 , Y10S428/901 , Y10T428/24917 , Y10T428/31522
摘要： The present invention provides a novel method of reducing the amount of seed deposited on polymeric dielectric surfaces. The method comprises the following steps: providing a work-piece coated with a polymeric dielectric layer; baking the work-piece to modify the surface of the polymeric dielectric layer; then applying the seed to polymeric dielectric layer and electrolessly plating metal to the seed layer. The invention also relates to a circuit board produced by the method of the present invention.

3. 发明授权

US06436803B1 Manufacturing computer systems with fine line circuitized substrates 有权
公开(公告)号：US06436803B1
公开(公告)日：2002-08-20
申请号：US09840432
申请日：2001-04-23
申请人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
发明人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
IPC分类号： H01L2144
摘要： Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.

4. 发明授权

US06268016B1 Manufacturing computer systems with fine line circuitized substrates 失效
标题翻译：制造具有细线电路化基板的计算机系统
公开(公告)号：US06268016B1
公开(公告)日：2001-07-31
申请号：US08672290
申请日：1996-06-28
申请人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
发明人： Anilkumar Chinuprasad Bhatt , Roy Harvey Magnuson , Thomas Richard Miller , Voya Rista Markovich , Carlos J. Sambucetti , Stephen Leo Tisdale
IPC分类号： B05D512
CPC分类号： H05K3/181 , C23C18/1632 , C23C18/2086 , H01L2224/16 , H01L2924/01046 , H01L2924/01078 , H01L2924/01322 , H01L2924/15312 , Y10T29/49126 , Y10T29/49165
摘要： Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring layer and via holes are formed through the dielectric layer over pads and conductors of the wiring layer. Holes are formed through the substrate and substrate surfaces including the photoimagable dielectric, walls of the via holes, and walls of the through holes subjected to an electroless copper plating process. The process includes seeding the surface, coating the surface with a first solution containing surfactant and electroplating in a second solution in which the level of surfactant is regulated by determining the surface tension and metering surfactant addition to the second solution depending on the determination of surface tension. The copper plating on the photoimagable dielectric is patterned to form an exterior wiring layer which is covered by solder resist with windows over lands around the through holes and surface mount connection pads of the exterior wiring layer to form a high density circuitized substrate. Surface mount components and/or pin in hole components are attached to the circuitized substrate with solder joints between terminals of the components and the lands and/or connection pads to form a high density circuit board assembly. One or more of the circuit board assemblies are mounted in an enclosure with a power supply, CPU, RAM, and I/O means to form an information handling system with increased performance due to shorter signal flight times due to the higher device density.
摘要翻译：通过形成具有电介质表面的基板并将金属箔层压到基板上来制造电路板。图案化金属箔以形成第一布线层。在布线层上方形成永久的光致可变电介质层，并且通过布线层的焊盘和导体上的电介质层形成通孔。通过基板和基板表面形成孔，包括可光成像的电介质，通孔的壁和穿过无电镀铜工艺的通孔的壁。该方法包括接种表面，用含有表面活性剂的第一溶液涂覆表面和在第二溶液中电镀，其中通过根据表面张力的测定确定表面张力和计量表面活性剂添加到第二溶液中来调节表面活性剂的含量。对可光成像电介质上的镀铜进行图案化以形成外部布线层，该外部布线层由通过孔周围的窗口和外部布线层的表面安装连接焊盘覆盖的阻焊剂覆盖，以形成高密度电路化基板。表面安装部件和/或销孔部件通过部件的端子与焊盘和/或连接焊盘之间的焊接点附接到电路化的基板，以形成高密度电路板组件。一个或多个电路板组件安装在具有电源，CPU，RAM和I / O装置的外壳中，由于更高的器件密度，由于更短的信号飞行时间，从而形成具有增加的性能的信息处理系统。

5. 发明授权

US5953594A Method of making a circuitized substrate for chip carrier structure 失效
标题翻译：制造用于芯片载体结构的电路化基板的方法
公开(公告)号：US5953594A
公开(公告)日：1999-09-14
申请号：US820995
申请日：1997-03-20
申请人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
发明人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
IPC分类号： H01L21/48 , H01L23/13 , H01L23/498 , H05K1/02 , H05K1/18 , H05K3/10 , H05K3/40 , H05K3/42 , H01L21/44
CPC分类号： H05K3/403 , H01L21/481 , H01L21/486 , H01L23/13 , H01L23/49805 , H01L24/49 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/854 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/15787 , H01L2924/3011 , H05K1/0203 , H05K1/021 , H05K1/182 , H05K2201/09127 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , H05K3/0061 , H05K3/108 , H05K3/427
摘要： An improved method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed, and at least one added layer of metallization is then applied to assure an entirely conductive opening between the member's opposing surfaces. The temporary support assures effective support for the dry film photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps. As taught herein, the entire sidewall portions defining the opening previously occupied by the temporary support portion are metallized to provide enhanced electrical characteristics for the finished product.
摘要翻译：制造可用作芯片载体结构的电路化衬底的改进方法。该方法包括提供电介质构件并部分地布置该构件以在其中限定临时支撑部分的步骤。然后可以发生金属化和电路化，随后除去临时支撑部分，然后施加至少一个附加的金属化层，以确保构件相对表面之间的完全导电的开口。临时支撑确保有效地支持用作电路化过程的一部分的干膜光致抗蚀剂。因此，光致抗蚀剂能够以片状形式施加以跨越电介质的相对小的开口而不会下垂，弯曲等，这可能不利地影响随后的处理步骤。如本文所教导的，限定先前由临时支撑部分占据的开口的整个侧壁部分被金属化以提供成品的增强的电特性。

6. 发明授权

US06570102B2 Structure for high speed printed wiring boards with multiple differential impedance-controlled layer 失效
公开(公告)号：US06570102B2
公开(公告)日：2003-05-27
申请号：US09878533
申请日：2001-06-11
申请人： Thomas Richard Miller , Konstantinos I. Papathomas , Brian Eugene Curcio , Joseph J. Sniezek
发明人： Thomas Richard Miller , Konstantinos I. Papathomas , Brian Eugene Curcio , Joseph J. Sniezek
IPC分类号： H01R1204
CPC分类号： H01L23/49822 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H05K1/0237 , H05K3/246 , H05K3/4069 , H05K3/4623 , H05K3/4652 , H05K2201/0347 , H05K2201/0352 , H05K2201/0355 , H05K2203/0554 , Y10T29/4913 , H01L2924/00
摘要： A method and arrangement for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, there are provided vias of either through-holes, blind holes and buried holes filled with a conductive paste material to form electrical interconnections with conductive layers of the printed wiring board.

7. 发明授权

US6063481A Process for removal of undersirable conductive material on a circuitized substrate and resultant circuitized substrate 失效
标题翻译：在电路化基板和合成电路化基板上去除不良导电材料的方法
公开(公告)号：US6063481A
公开(公告)日：2000-05-16
申请号：US36065
申请日：1998-03-06
申请人： Edward Lee Arrington , John Christopher Camp , Robert Jeffrey Day , Edmond Otto Fey , Curtis Michael Gunther , Thomas Richard Miller
发明人： Edward Lee Arrington , John Christopher Camp , Robert Jeffrey Day , Edmond Otto Fey , Curtis Michael Gunther , Thomas Richard Miller
IPC分类号： H05K3/18 , H05K3/26 , B32B3/00 , B32B15/04
CPC分类号： H05K3/26 , H05K3/184 , H05K2201/0761 , H05K2203/0796 , Y10S428/901 , Y10T428/12396 , Y10T428/12715 , Y10T428/12861 , Y10T428/12868 , Y10T428/24917
摘要： A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g., with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e.g., with a cyanide submersion). The resultant circuitized substrate includes a circuit pattern on a catalyst layer wherein undesirable portions of the catalyst layer and circuit pattern are completely removed between the circuit features of the circuit pattern so that electrical leakage between the circuit features does not occur.
摘要翻译：用于去除电路化基板上的不期望的导电材料（例如催化剂材料和渗出的电路材料）的方法以及公开的所得的电路化基板。这种工艺和结果电路有效地解决了残余催化剂材料和残余催化剂材料下渗出的电路材料的非破坏所引起的电短路问题。该方法包括以下步骤：a）在其上提供具有电路图案（例如铜）的催化剂层（例如钯和锡） b）预处理催化剂层和电路图案（例如，用氰化物浸渍），以除去在电路图案的电路线之间引起漏电的各部分的不希望的部分; c）氧化催化剂层和电路图案（例如，在高于环境条件的温度下使用亚氯酸盐，高锰酸盐，过氧化氢或空气）; 以及d）去除催化剂层的不期望的部分和电路图案的不希望的部分（例如，氰化物浸没）。所得到的电路化衬底包括在催化剂层上的电路图案，其中在电路图案的电路特征之间催化剂层和电路图案的不期望部分被完全去除，使得电路特征之间的电泄漏不会发生。

8. 发明授权

US06225028B1 Method of making an enhanced organic chip carrier package 失效
标题翻译：制造增强型有机芯片载体封装的方法
公开(公告)号：US06225028B1
公开(公告)日：2001-05-01
申请号：US09482548
申请日：2000-01-13
申请人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
发明人： Anilkumar Chinuprasad Bhatt , Thomas Richard Miller , Allen Frederick Moring , James Paul Walsh
IPC分类号： G03F700
CPC分类号： H01L23/13 , H01L21/481 , H01L21/486 , H01L23/49805 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01013 , H01L2924/01028 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H05K1/0203 , H05K1/021 , H05K1/182 , H05K3/0061 , H05K3/064 , H05K3/108 , H05K3/403 , H05K3/427 , H05K2201/09127 , H05K2203/0191 , H05K2203/0264 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.
摘要翻译：一种制造电路化基板的方法，其中与形成基板电路的一部分的多个导电元件（例如，焊盘，线等）一起形成芯片容纳腔。通过使用允许其牺牲层的初始去除（剥离），然后最终去除也成为该部件的一部分的光成像层，可以实现金属化。光成像层的曝光可以通过保护性牺牲层或随后的去除而发生。

9. 发明授权

US06815126B2 Printed wiring board with conformally plated circuit traces 失效
标题翻译：印刷电路板，带有电镀电路迹线
公开(公告)号：US06815126B2
公开(公告)日：2004-11-09
申请号：US10119489
申请日：2002-04-09
申请人： Edmond Otto Fey , Raymond Thomas Galasco , Thomas Richard Miller , Anita Sargent
发明人： Edmond Otto Fey , Raymond Thomas Galasco , Thomas Richard Miller , Anita Sargent
IPC分类号： G03F700
CPC分类号： H05K3/242 , C25D7/123 , H05K3/0052 , H05K3/243 , H05K3/28 , H05K3/428 , H05K2203/054 , H05K2203/0542
摘要： A PWB or multilayer board with circuit traces is treated by a process that serves to reduce the incident of failure of the board. The process includes the steps of applying a thin commoning layer of copper onto a catalyzed surface of the board substrate and the circuit lines. A photoresist is then applied over the commoning layer after which the photoresist is removed only from the commoning material over the circuit lines. A thin layer of a more noble metal, such as nickel, is electrodeposited over the exposed conductive layer. This is followed by a gold layer electrodeposited over the nickel in close registry therewith. The process provides the traces with a conforming nickel/gold layer that extends down the side of the traces. This reduces the tendency of a subsequent copper etch step from undercutting the nickel/gold, thereby causing slivers that could cause short circuiting between adjacent circuit patterns.
摘要翻译：具有电路迹线的PWB或多层板被用于减少电路板故障事故的过程来处理。该方法包括以下步骤：将铜的薄共同层施加到板基板和电路线的催化表面上。然后将光致抗蚀剂施加在共用层上，之后仅通过电路线从普通材料除去光致抗蚀剂。更贵的金属如镍的薄层电沉积在暴露的导电层上。之后是电沉积在镍上的金层与其紧密对准。该工艺为痕迹提供了沿着迹线侧面延伸的一致的镍/金层。这降低了随后的铜蚀刻步骤从底切镍/金的趋势，从而导致可能导致相邻电路图案之间短路的条子。

10. 发明授权

US06544584B1 Process for removal of undesirable conductive material on a circuitized substrate and resultant circuitized substrate 失效
标题翻译：在电路化基板和合成电路化基板上去除不需要的导电材料的工艺
公开(公告)号：US06544584B1
公开(公告)日：2003-04-08
申请号：US08813765
申请日：1997-03-07
申请人： Edward Lee Arrington , John Christopher Camp , Robert Jeffrey Day , Edmond Otto Fey , Curtis Michael Gunther , Thomas Richard Miller
发明人： Edward Lee Arrington , John Christopher Camp , Robert Jeffrey Day , Edmond Otto Fey , Curtis Michael Gunther , Thomas Richard Miller
IPC分类号： B05D512
CPC分类号： H05K3/26 , H05K3/184 , H05K2201/0761 , H05K2203/0796 , Y10S428/901 , Y10T428/12396 , Y10T428/12715 , Y10T428/12861 , Y10T428/12868 , Y10T428/24917 , Y10T428/31678
摘要： A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g., with chlorite, permanganate, hydrogen peroxide, or air at a temperature elevated above ambient conditions); and d) removing the undesirable portions of the catalyst layer and the undesirable portions of the circuit pattern (e.g., with a cyanide submersion). The resultant circuitized substrate includes a circuit pattern on a catalyst layer wherein undesirable portions of the catalyst layer and circuit pattern are completely removed between the circuit features of the circuit pattern so that electrical leakage between the circuit features does not occur.
摘要翻译：用于去除电路化基板上的不期望的导电材料（例如催化剂材料和渗出的电路材料）的方法以及公开的所得的电路化基板。这种工艺和结果电路有效地解决了残余催化剂材料和残余催化剂材料下渗出的电路材料的非破坏所引起的电短路问题。该方法包括以下步骤：a）在其上提供具有电路图案（例如铜）的催化剂层（例如钯和锡） b）预处理催化剂层和电路图案（例如，用氰化物浸渍），以除去在电路图案的电路线之间引起漏电的各部分的不希望的部分; c）氧化催化剂层和电路图案（例如，在高于环境条件的温度下使用亚氯酸盐，高锰酸盐，过氧化氢或空气）; 以及d）去除催化剂层的不期望的部分和电路图案的不希望的部分（例如，氰化物浸没）。所得到的电路化衬底包括在催化剂层上的电路图案，其中在电路图案的电路特征之间催化剂层和电路图案的不期望部分被完全去除，使得电路特征之间的电泄漏不会发生。

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