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    • 5. 发明授权
    • Methods and apparatus for ManArray PE-PE switch control
    • ManArray PE-PE开关控制的方法和装置
    • US06795909B2
    • 2004-09-21
    • US10114646
    • 2002-04-01
    • Edwin F. BarryGerald G. PechanekThomas L. DrabenstottEdward A. WolffNikos P. PitsianisGrayson Morris
    • Edwin F. BarryGerald G. PechanekThomas L. DrabenstottEdward A. WolffNikos P. PitsianisGrayson Morris
    • G06F1517
    • G06F15/17381H04L49/1553H04L49/201H04L49/3009H04L49/45
    • Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
    • 使用接收模型描述处理元件切换连接控制的处理元件,该接收模型排除在同步MIMD操作模式中发生通信危险。 这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果,例如阵列转置,超补充等。 编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。 因此,通过基于由PE通信指令指定的通信路径变换PE标识,可以使用有效的开关控制机构。 该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG,SPRECV和SPSEND也被定义和实现。
    • 6. 发明授权
    • Methods and apparatus for manarray PE-PE switch control
    • 用于管理PE-PE开关控制的方法和装置
    • US06366997B1
    • 2002-04-02
    • US09649647
    • 2000-08-29
    • Edwin F. BarryGerald G. PechanekThomas L. DrabenstottEdward A. WolffNikos P. PitsianisGrayson Morris
    • Edwin F. BarryGerald G. PechanekThomas L. DrabenstottEdward A. WolffNikos P. PitsianisGrayson Morris
    • G06F1576
    • G06F15/17381H04L49/1553H04L49/201H04L49/3009H04L49/45
    • Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
    • 使用接收模型描述处理元件切换连接控制的处理元件,该接收模型排除在同步MIMD操作模式中发生通信危险。 这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果,例如阵列转置,超补充等。 编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。 因此,通过基于由PE通信指令指定的通信路径变换PE标识,可以使用有效的开关控制机构。 该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG,SPRECV和SPSEND也被定义和实现。
    • 7. 发明授权
    • Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
    • 在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
    • US06760831B2
    • 2004-07-06
    • US10114652
    • 2002-04-01
    • Thomas L. DrabenstottGerald G. PechanekEdwin F. BarryCharles W. Kurak, Jr.
    • Thomas L. DrabenstottGerald G. PechanekEdwin F. BarryCharles W. Kurak, Jr.
    • G06F1580
    • G06F9/30094G06F9/30036G06F9/30072G06F9/30181G06F9/3842G06F9/3885G06F9/3887G06F9/3891G06F15/8007
    • General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
    • 使用分层一位,二位或三位编码来定义和编码通用标志(ACF)。 每个添加的位提供了先前功能的超集。 通过条件组合,可以避免基于复杂条件的顺序一系列条件分支,然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。 通过改变受影响的标志的数量,条件操作并行性可以被广泛地变化,例如,从VLIW执行中的单处理到八进制处理,以及处理元件(PE)的阵列。 多个PE可以同时生成条件信息,程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。 多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。