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1. 再颁专利

USRE41703E1 Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication 有权
标题翻译：用于IVLIW PE-TO-PE通信的高效同步MIMD操作的方法和装置
公开(公告)号：USRE41703E1
公开(公告)日：2010-09-14
申请号：US10872995
申请日：2004-06-21
申请人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
发明人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.
摘要翻译：使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。可以使用掩蔽机制来控制哪些PE装载有VIM。此外，优选采用操作的接收模式。在一个方面，每个PE操作以控制从其接收的PE选择的交换机。本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

2. 发明授权

US07266620B1 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US07266620B1
公开(公告)日：2007-09-04
申请号：US10797726
申请日：2004-03-10
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.
摘要翻译：描述具有将数据从外部设备传送到内部存储器的内部存储器的系统核心。为此，系统核心包括处理器，直接存储器访问（DMA）控制器，指令存储器和多个存储器。指令存储器包含处理器指令和DMA指令。 DMA控制器从指令存储器中获取DMA指令。 DMA控制器执行所提取的DMA指令，并且由此来自外部设备的数据填充多个存储器。然后，处理器对在填充的存储器中找到的数据进行操作。

3. 发明授权

US07257696B2 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 有权
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US07257696B2
公开(公告)日：2007-08-14
申请号：US10641441
申请日：2003-08-15
申请人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/302
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

4. 发明授权

US07506137B2 Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions 失效
标题翻译：用于启动和重新同步多周期SIMD指令的方法和装置
公开(公告)号：US07506137B2
公开(公告)日：2009-03-17
申请号：US11778303
申请日：2007-07-16
申请人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
发明人： Gerald George Pechanek , David Strube , Edward A. Wolff , Edwin Franklin Barry , Grayson Morris , Carl Donald Busboom , Dale Edward Schneider
IPC分类号： G06F9/302
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30149 , G06F9/325 , G06F9/3836 , G06F9/3853 , G06F9/3857 , G06F9/3859 , G06F9/3887
摘要： Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.
摘要翻译：描述了使用单指令多数据流（SIMD）非常长的指令字（VLIW）处理框架来添加更复杂指令的技术及其伴随的多周期执行单元。在一个方面，启动机制还充当重新同步机制以读取多周期执行的结果。该多用途机构以单循环指令的短指令字（SIW）问题，单独的序列处理器（SP），VLIW以及跨所有处理元件（PE）单独地或作为PE阵列来操作。还描述了许多有利的浮点指令。

5. 发明授权

US08397000B2 System core for transferring data between an external device and memory 失效
公开(公告)号：US08397000B2
公开(公告)日：2013-03-12
申请号：US13611969
申请日：2012-09-12
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

6. 发明申请

US20140059324A1 System Core for Transferring Data Between an External Device and Memory 审中-公开
标题翻译：用于在外部设备和内存之间传输数据的系统核心
公开(公告)号：US20140059324A1
公开(公告)日：2014-02-27
申请号：US13771390
申请日：2013-02-20
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo Rodriguez , Marco Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, JR. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo Rodriguez , Marco Jacobs
IPC分类号： G06F15/82
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

7. 发明授权

US08296479B2 System core for transferring data between an external device and memory 有权
标题翻译：用于在外部设备和存储器之间传输数据的系统核心
公开(公告)号：US08296479B2
公开(公告)日：2012-10-23
申请号：US13344339
申请日：2012-01-05
申请人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
发明人： Gerald George Pechanek , David Strube , Edwin Franklin Barry , Charles W. Kurak, Jr. , Carl Donald Busboom , Dale Edward Schneider , Nikos P. Pitsianis , Grayson Morris , Edward A. Wolff , Patrick R. Marchand , Ricardo E. Rodriguez , Marco C. Jacobs
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F15/82 , G06F9/30145 , G06F11/263 , Y10S707/99943
摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.
摘要翻译：这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。可以很容易地映射参数化，并显着简化系统维护。

8. 发明授权

US07680873B2 Methods and apparatus for efficient complex long multiplication and covariance matrix implementation 失效
公开(公告)号：US07680873B2
公开(公告)日：2010-03-16
申请号：US11438418
申请日：2006-05-22
申请人： Gerald George Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
发明人： Gerald George Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
IPC分类号： G06F7/52
CPC分类号： G06F7/4812 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F17/15 , G06F17/16 , G06F2207/3896
摘要： Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

9. 发明授权

US09075651B2 Methods and apparatus for efficient complex long multiplication and covariance matrix implementation 有权
公开(公告)号：US09075651B2
公开(公告)日：2015-07-07
申请号：US13613769
申请日：2012-09-13
申请人： Gerald George Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
发明人： Gerald George Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
IPC分类号： G06F17/15 , G06F17/16 , G06F9/30 , G06F7/48 , G06F9/32 , G06F9/38
CPC分类号： G06F7/4812 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F17/15 , G06F17/16 , G06F2207/3896
摘要： Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

10. 发明授权

US07237088B2 Methods and apparatus for providing context switching between software tasks with reconfigurable control 有权
标题翻译：用于通过可重新配置的控制在软件任务之间提供上下文切换的方法和装置
公开(公告)号：US07237088B2
公开(公告)日：2007-06-26
申请号：US10761564
申请日：2004-01-21
申请人： Edwin Franklin Barry , Gerald George Pechanek , David Strube
发明人： Edwin Franklin Barry , Gerald George Pechanek , David Strube
IPC分类号： G06F15/80
CPC分类号： G06F9/30181 , G06F9/30043 , G06F9/30076 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/462 , G06F15/8007
摘要： The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the SP/PE-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array SP/PE-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file. In arrays consisting of more than a single PE, the software controllable context switch mechanism is used to reconfigure the array to take advantage of the multiple context support the merged SP/PE provides. For example, a 1×1 can be configured as a 1×1 with context-0 and as a 1×0 with context-1, a 1×2 can be configured as a 1×2 with context-0 and as a 1×1 with context-1, and a 1×5 can be configured as a 1×5 with context-0 and as a 2×2 with context-1. Other array configurations are clearly possible using the present techniques. In the 1×5/2×2 case, the two contexts could be a 1×5 array (context-0) and a 2×2 array (context-1).
摘要翻译： ManArray核心间接VLIW处理器由阵列控制器序列处理器（SP）组成，与处理元件（PE0）合并，该处理元件（PE0）将SP与PE阵列紧密耦合，并提供在SP和PE0之间共享执行单元的能力。因此，在合并的SP / PE0中，单个执行单元集合与两个独立的寄存器文件耦合。为了有效利用SP和PE资源，ManArray架构规定了指令格式（SP / PE位）的一点，以区分SP指令和PE指令。通过控制ManArray指令格式中的阵列SP / PE位如何与用于PE寄存器文件或SP寄存器文件的上下文选择的上下文切换位（CSB）结合使用，在ManArray处理器中获得多个寄存器上下文。在由多个单独的PE组成的阵列中，软件可控上下文切换机制用于重新配置阵列，以利用合并的SP / PE提供的多个上下文支持。例如，1x1可以被配置为具有上下文0的1x1和具有上下文-1的1x0，1x2可以被配置为具有上下文-1的1x2和具有上下文-1的1x1，并且1x5可以被配置为具有上下文-1的1x2 配置为具有上下文0的1x5和具有上下文-1的2x2。使用本技术可以清楚地看出其它阵列配置。在1x5 / 2x2情况下，两个上下文可能是1x5阵列（上下文0）和2x2阵列（上下文-1）。

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