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1. 发明授权

US07991955B2 Method and apparatus to achieve more level thermal gradient 有权
标题翻译：实现更多级别热梯度的方法和装置
公开(公告)号：US07991955B2
公开(公告)日：2011-08-02
申请号：US11610379
申请日：2006-12-13
申请人： Michael D. Bienek , Victor F. Andrade , Randal L. Posey , Michael C. Braganza
发明人： Michael D. Bienek , Victor F. Andrade , Randal L. Posey , Michael C. Braganza
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0864
摘要： Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.
摘要翻译：在进行老化的同时，在集成电路上实现更好的温度均匀性可以减少老化时间和更均匀的加速。实现更好的温度均匀性的一种方式是通过在不同频率下操作来控制核心和高速缓存中的动态功率，并且通过改变高速缓存的操作来增加在高速缓存期间的高速缓存中的切换活动，使得在老化多个高速缓存中的存储器位置被同时访问，从而增加高速缓存中的活动以在老化期间在高速缓存中实现更高的功率利用。

2. 发明申请

US20080147976A1 METHOD AND APPARATUS TO ACHIEVE MORE LEVEL THERMAL GRADIENT 有权
标题翻译：实现更高等级热梯度的方法和装置
公开(公告)号：US20080147976A1
公开(公告)日：2008-06-19
申请号：US11610379
申请日：2006-12-13
申请人： Michael D. Bienek , Victor F. Andrade , Randal L. Posey , Michael C. Braganza
发明人： Michael D. Bienek , Victor F. Andrade , Randal L. Posey , Michael C. Braganza
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0864
摘要： Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.
摘要翻译：在进行老化的同时，在集成电路上实现更好的温度均匀性可以减少老化时间和更均匀的加速。实现更好的温度均匀性的一种方式是通过在不同频率下操作来控制核心和高速缓存中的动态功率，并且通过改变高速缓存的操作来增加在高速缓存期间的高速缓存中的切换活动，使得在老化多个高速缓存中的存储器位置被同时访问，从而增加高速缓存中的活动以在老化期间在高速缓存中实现更高的功率利用。

3. 发明授权

US07355881B1 Memory array with global bitline domino read/write scheme 有权
标题翻译：具有全局位线多米诺骨牌读/写方案的内存阵列
公开(公告)号：US07355881B1
公开(公告)日：2008-04-08
申请号：US11285670
申请日：2005-11-22
申请人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
发明人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/1051 , G11C7/1057 , G11C7/12 , G11C2207/002
摘要： A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.
摘要翻译：使用全局位线多米诺读/写方案实现存储器阵列的电路。存储器电路包括多个单元，每个单元被配置为存储一位数据。存储器电路还包括多个本地位线，其中每个单元耦合到本地位线之一。多个本地位线中的每一个是具有由一对晶体管交叉耦合的信号路径和互补信号路径的差分位线。

4. 发明授权

US06622225B1 System for minimizing memory bank conflicts in a computer system 有权
标题翻译：用于最小化计算机系统中的存储器组冲突的系统
公开(公告)号：US06622225B1
公开(公告)日：2003-09-16
申请号：US09652325
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to different memory banks. Memory bank conflicts are avoided by examining each transaction before it is loaded in the memory transaction queue. On a first clock cycle, the new pending memory request is transferred from a pending request queue to a memory mapper. On the subsequent clock cycle, the memory mapper formats the pending memory request into separate signals identifying the DEVICE, BANK, ROW and COLUMN to be accessed by the pending transaction. In the next clock cycle, the DEVICE and BANK signals are compared with every entry in the memory transaction queue to determine if a bank conflict exists. If so, the new memory request is rejected and recycled to the pending request queue.
摘要翻译：计算机系统包括将处理器与存储器系统接口的存储器控制器。存储器控制器支持具有多个存储器设备的存储器系统，每个存储器设备中具有多个存储体。存储器控制器支持对不同存储体的同时存储器访问。通过在每个事务加载到内存事务队列中之前检查每个事务来避免存储器组冲突。在第一个时钟周期中，新的挂起的存储器请求从挂起的请求队列传送到存储器映射器。在随后的时钟周期中，存储器映射器将待处理的存储器请求格式化成单独的信号，标识要由待处理事务访问的DEVICE，BANK，ROW和COLUMN。在下一个时钟周期中，将DEVICE和BANK信号与存储器事务队列中的每个条目进行比较，以确定是否存在存储库冲突。如果是这样，新的内存请求被拒绝并被回收到挂起的请求队列。

5. 发明授权

US06546453B1 Proprammable DRAM address mapping mechanism 失效
标题翻译：可预测的DRAM地址映射机制
公开(公告)号：US06546453B1
公开(公告)日：2003-04-08
申请号：US09653093
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Peter J. Bannon , Michael C. Braganza , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Peter J. Bannon , Michael C. Braganza , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0882 , G06F12/0215 , G06F12/0607
摘要： A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield. This diminishes page misses caused by replacement of data blocks from the cache memory because the read of the new data block and write of the victim data block are not to the same memory bank. Adjacent memory bank conflicts are reduced for sequential accesses to memory banks by reversing the bit order of a bank number subfield within the bank subfield of the device address.
摘要翻译：计算机系统包含包括软件可编程存储器映射器的处理器。存储器映射器将由处理器生成的地址映射到用于访问物理主存储器的设备地址。处理器还包括将处理器地址映射到高速缓存地址的高速缓存控制器。高速缓存地址使用索引子字段将主存储器的数据块放入存储器高速缓存。物理主存储器包含RDRAM设备，每个RDRAM设备包含存储行和数据列的多个存储器组。内存映射器将处理器地址映射到设备地址，以提高内存系统性能。该映射最小化了存储体之间的存储器访问冲突。通过将对应于银行子字段的多个位放置在索引子字段的最高有效边界位之上来减少存储体之间的冲突。由于新数据块的读取和受害者数据块的写入不是同一个存储体，这会减少由高速缓冲存储器替换数据块所造成的页面错误。通过反转设备地址的银行子字段内的库号子字段的位顺序，减少了对存储体的顺序访问的相邻存储体冲突。

6. 发明授权

US06714464B2 System and method for a self-calibrating sense-amplifier strobe 有权
标题翻译：用于自校准读出放大器选通的系统和方法
公开(公告)号：US06714464B2
公开(公告)日：2004-03-30
申请号：US10180478
申请日：2002-06-26
申请人： Ajay Bhatia , Michael C. Braganza , Shannon V. Morton , Shashank Shastry
发明人： Ajay Bhatia , Michael C. Braganza , Shannon V. Morton , Shashank Shastry
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/06 , G11C7/22 , G11C2207/065 , G11C2207/2254
摘要： A system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.
摘要翻译：用于RAM阵列的读出放大器的选通定时的自校准的系统和方法。在一个方法示例中，用于读取RAM阵列的位线的两个读出放大器的定时由延迟锁定环电路（DLL）控制。第一感测放大器选通脉冲的定时降低，直到读出放大器发生故障。然而，第二感测放大器具有足够的定时裕度，并用于实际读取RAM位线。一旦RAM读取失败，第一个读出放大器，DLL会延长选通时序。一旦设置了最小阈值，由于第一和第二放大器之间的内置定时裕度，第二读出放大器将始终读取正确的数据。因此，即使最小时间变化，系统也会随着每个读取周期不断优化RAM阵列读取定时。

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