专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07496861B2 Method for generalizing design attributes in a design capture environment 失效
标题翻译：在设计捕获环境中概括设计属性的方法
公开(公告)号：US07496861B2
公开(公告)日：2009-02-24
申请号：US11290186
申请日：2005-11-30
申请人： George W. Nation , Gary Lippert , Gary S. Delp
发明人： George W. Nation , Gary Lippert , Gary S. Delp
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.
摘要翻译：一种用于在设计捕获环境中概括设计属性的方法，包括以下步骤：（A）定义用于将一个或多个辅助配置器添加到工具或工具套件的过程，（B）将辅助配置器链接到抽象的预定对象点设计和（C）定义用于参考一个或多个辅助配置器的工具或工具套件的过程，其中辅助配置器既不被核心引用也不内置在工具或工具套件中。

2. 发明授权

US07043703B2 Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers 有权
标题翻译：使用输入/输出关联区域的灵活使用硬宏I / O缓冲区的架构和/或方法
公开(公告)号：US07043703B2
公开(公告)日：2006-05-09
申请号：US10241317
申请日：2002-09-11
申请人： George W. Nation , Gary S. Delp
发明人： George W. Nation , Gary S. Delp
IPC分类号： G06F17/50
CPC分类号： G06F1/22
摘要： An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.
摘要翻译：一种装置，包括（i）一个或多个输入/输出单元，（ii）一个或多个硬宏和（iii）一个或多个输入/输出相关区域。一个或多个输入/输出亲和度区域可以设置在一个或多个输入/输出单元与一个或多个硬宏之间。一个或多个输入/输出关联区域中的每一个可以被定制为（i）第一模式中的电路，以及（ii）在第二模式中在一个或多个输入/输出单元与一个或多个硬宏之间进行路由选择。

3. 发明授权

US06966044B2 Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources 失效
标题翻译：用于在可编程平台设备上组合存储器的方法，以通过固定的资源来满足不同的存储器要求
公开(公告)号：US06966044B2
公开(公告)日：2005-11-15
申请号：US10316101
申请日：2002-12-09
申请人： Paul G. Reuland , George W. Nation , Jonathan Byrn , Gary S. Delp
发明人： Paul G. Reuland , George W. Nation , Jonathan Byrn , Gary S. Delp
IPC分类号： G06F17/50 , H01L21/82 , H01L27/10 , H03K19/00
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.
摘要翻译：一种用于在可编程平台设备上组合存储器的方法，包括以下步骤：（A）接受关于包括一个或多个扩散存储器区域和一个或多个门阵列区域的可编程平台设备的信息; （B）接受一个或多个存储器的预定设计信息; 和（C）在一个或多个扩散存储区域中组成一个或多个存储器构建块（i），（ii）在一个或多个门阵列区域中，或（iii）基于扩散存储器和门阵列区域预定的设计信息和有关可编程平台设备的信息。

4. 发明授权

US07043611B2 Reconfigurable memory controller 有权
标题翻译：可重构内存控制器
公开(公告)号：US07043611B2
公开(公告)日：2006-05-09
申请号：US10316510
申请日：2002-12-11
申请人： Gary P. McClannahan , Gary S. Delp , George W. Nation
发明人： Gary P. McClannahan , Gary S. Delp , George W. Nation
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.
摘要翻译：可重构存储器控制器包括多个通信耦合的存储器控制器。可以基于存储器控制器的分组将多个存储器控制器配置为第一配置，然后基于存储器控制器的不同组合重新配置成第二配置，其中第一和第二配置具有用于访问存储器的不同的性能带宽。

5. 发明授权

US08484608B2 Base platforms with combined ASIC and FPGA features and process of using the same 失效
公开(公告)号：US08484608B2
公开(公告)日：2013-07-09
申请号：US12576775
申请日：2009-10-09
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

6. 发明授权

US07405476B2 Asymmetric alignment of substrate interconnect to semiconductor die 有权
标题翻译：衬底互连对半导体裸片的不对称对准
公开(公告)号：US07405476B2
公开(公告)日：2008-07-29
申请号：US11260334
申请日：2005-10-27
申请人： Gary S. Delp
发明人： Gary S. Delp
IPC分类号： H01L23/34
CPC分类号： H01L23/5386 , H01L24/81 , H01L25/0655 , H01L2224/24226 , H01L2224/81801 , H01L2224/82 , H01L2224/85 , H01L2224/86 , H01L2924/14 , H01L2924/00
摘要： An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
摘要翻译：一种装置包括第一半导体管芯和至少一个另外的半导体管芯。衬底附接到第一裸片和另一裸片，并且具有将第一裸片上的触点与另一裸片上的相应触点互连的电互连图案。互连图案的特征在基板上具有相对于第一裸片上的触点的位置具有比在另一裸片上的触点的位置更小的公差的位置。

7. 发明授权

US5752078A System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory 失效
标题翻译：将数据包从适配器存储器传输到主机存储器时检测到的系统，用于最小化延迟数据接收和处理数据包错误
公开(公告)号：US5752078A
公开(公告)日：1998-05-12
申请号：US500491
申请日：1995-07-10
申请人： Gary S. Delp , Philip L. Leichty , Albert A. Slane
发明人： Gary S. Delp , Philip L. Leichty , Albert A. Slane
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , G06F13/128 , H04L49/90
摘要： A method and system within a data processing system are disclosed for receiving information from a communications network. The data processing system includes a communications adapter, having an adapter memory, and a host memory. The communications adapter is coupled to the communications network, which transmits information to the data processing system in packets including a packet header and packet data. According to the present invention, a portion of a packet of information is received from the communications network at the adapter memory within the communications adapter. The portion of the packet of information includes at least a packet header that specifies a length of the packet of information and a destination address within the host memory. In response to receipt of the portion of the packet of information, a transfer of the packet of information from the adapter memory to the host memory is prepared prior to receipt of a final portion of the packet of information at the adapter memory. The packet of information is then transferred from the adapter memory to addresses within the host memory beginning with the destination address. Since the transfer is prepared before packet receipt is complete, perceived latency is minimized.
摘要翻译：公开了一种用于从通信网络接收信息的数据处理系统内的方法和系统。数据处理系统包括具有适配器存储器和主机存储器的通信适配器。通信适配器耦合到通信网络，其以包括分组报头和分组数据的分组向数据处理系统发送信息。根据本发明，从通信适配器内的适配器存储器处的通信网络接收信息分组的一部分。信息分组的部分至少包括指定信息分组的长度的分组报头和主机存储器内的目的地地址。响应于接收到信息分组的一部分，在适配器存储器上接收到信息分组的最后部分之前准备将信息分组从适配器存储器传送到主机存储器。然后将信息包从适配器存储器转移到主目录内的地址，以目的地址开始。由于在分组接收完成之前准备传输，所以感知到的等待时间被最小化。

8. 发明授权

US5598535A System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions 失效
标题翻译：系统用于在不存在异常情况时，对来自不同会话的数据包进行选择性和累积分组，并在预选的时间条件之后发送数据包
公开(公告)号：US5598535A
公开(公告)日：1997-01-28
申请号：US283889
申请日：1994-08-01
申请人： Brad L. Brech , Gary S. Delp , Albert A. Slane
发明人： Brad L. Brech , Gary S. Delp , Albert A. Slane
IPC分类号： H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： H04L29/06 , H04L69/22 , H04L69/32
摘要： The present invention provides a method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.
摘要翻译：本发明提供一种用于增强在数据处理系统内以逻辑单元接收的多个相关分组的处理的方法和装置处理系统。在逻辑单元处接收多个分组。然后检查多个分组中的每一个，并且为多个分组中的每个分组获得会话标识。在预选时间窗口期间，多个分组中的每一个与组相关联。组中的每个分组具有与组内的每个其他分组相同的会话标识。

9. 发明授权

US5629933A Method and system for enhanced communication in a multisession packet based communication system 失效
标题翻译：用于在基于多业务分组的通信系统中增强通信的方法和系统
公开(公告)号：US5629933A
公开(公告)日：1997-05-13
申请号：US472368
申请日：1995-06-07
申请人： Gary S. Delp , Albert A. Slane
发明人： Gary S. Delp , Albert A. Slane
IPC分类号： H04L12/56 , H04L29/08 , H04Q11/04 , H04J3/24
CPC分类号： H04L49/9047 , H04L47/19 , H04L49/90 , H04L49/901 , H04L67/14
摘要： The method and system for enhanced efficiency in a multisession communication system which utilizes a series of data packets wherein each data packet includes an indication of the identity of a particular session to which that data packet belongs. Each received data packet is examined as that data packet is received to determine a session identity for that packet. An indication of the session identity is thereafter listed within a session queue only in response to an initial occurrence of that session identity. Each data packet for a listed session identity is then stored in a data packet queue in First-In First-Out (FIFO) order which is associated with the listed session identity wherein all packets for a session remain in order, even though the overall order of all packets may be enhanced. In this manner all data packets within a particular session may be efficiently accessed for processing or, alternatively, one or more data packets within each session may be accessed serially for processing in a round-robin fashion.
摘要翻译：一种利用一系列数据分组的多业务通信系统中提高效率的方法和系统，其中每个数据分组包括该数据分组所属的特定会话的标识的指示。当接收到数据包以确定该分组的会话标识时，检查每个接收到的数据分组。会话身份的指示此后仅在会话队列中列出，仅响应于该会话身份的初始出现。然后，列出的会话标识的每个数据分组以先入先出（FIFO）顺序存储在与列出的会话标识相关联的数据分组队列中，其中所有会话的分组都保持顺序，即使整体顺序可以增强所有分组。以这种方式，可以有效地访问特定会话内的所有数据分组以进行处理，或者替代地，可以串行地访问每个会话内的一个或多个数据分组以循环方式进行处理。

10. 发明授权

US5533020A ATM cell scheduler 失效
标题翻译： ATM信元调度器
公开(公告)号：US5533020A
公开(公告)日：1996-07-02
申请号：US332160
申请日：1994-10-31
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
IPC分类号： G06F13/00 , H04L12/56 , H04L29/06 , H04L29/08 , H04Q3/00 , H04Q11/04
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5635 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679
摘要： A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.
摘要翻译：一种用于通过公共通信链路调度多个数据流的传输的方法和装置，其中每个数据流符合对应的一组流量控制参数。要在通信链路上发送的每个数据流都存储在相应的队列中。维护每个队列的状态，并计算每个队列的目标传输时间。然后至少在目标传输时间之后，每个队列生成信号，并且这些信号用于指示可以在链路上传送单元的相应队列。在接收到对应信号时，队列随后将至少一个小区发送到通信链路上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式