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1. 发明授权

US5629933A Method and system for enhanced communication in a multisession packet based communication system 失效
标题翻译：用于在基于多业务分组的通信系统中增强通信的方法和系统
公开(公告)号：US5629933A
公开(公告)日：1997-05-13
申请号：US472368
申请日：1995-06-07
申请人： Gary S. Delp , Albert A. Slane
发明人： Gary S. Delp , Albert A. Slane
IPC分类号： H04L12/56 , H04L29/08 , H04Q11/04 , H04J3/24
CPC分类号： H04L49/9047 , H04L47/19 , H04L49/90 , H04L49/901 , H04L67/14
摘要： The method and system for enhanced efficiency in a multisession communication system which utilizes a series of data packets wherein each data packet includes an indication of the identity of a particular session to which that data packet belongs. Each received data packet is examined as that data packet is received to determine a session identity for that packet. An indication of the session identity is thereafter listed within a session queue only in response to an initial occurrence of that session identity. Each data packet for a listed session identity is then stored in a data packet queue in First-In First-Out (FIFO) order which is associated with the listed session identity wherein all packets for a session remain in order, even though the overall order of all packets may be enhanced. In this manner all data packets within a particular session may be efficiently accessed for processing or, alternatively, one or more data packets within each session may be accessed serially for processing in a round-robin fashion.
摘要翻译：一种利用一系列数据分组的多业务通信系统中提高效率的方法和系统，其中每个数据分组包括该数据分组所属的特定会话的标识的指示。当接收到数据包以确定该分组的会话标识时，检查每个接收到的数据分组。会话身份的指示此后仅在会话队列中列出，仅响应于该会话身份的初始出现。然后，列出的会话标识的每个数据分组以先入先出（FIFO）顺序存储在与列出的会话标识相关联的数据分组队列中，其中所有会话的分组都保持顺序，即使整体顺序可以增强所有分组。以这种方式，可以有效地访问特定会话内的所有数据分组以进行处理，或者替代地，可以串行地访问每个会话内的一个或多个数据分组以循环方式进行处理。

2. 发明授权

US5752078A System for minimizing latency data reception and handling data packet error if detected while transferring data packet from adapter memory to host memory 失效
标题翻译：将数据包从适配器存储器传输到主机存储器时检测到的系统，用于最小化延迟数据接收和处理数据包错误
公开(公告)号：US5752078A
公开(公告)日：1998-05-12
申请号：US500491
申请日：1995-07-10
申请人： Gary S. Delp , Philip L. Leichty , Albert A. Slane
发明人： Gary S. Delp , Philip L. Leichty , Albert A. Slane
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , G06F13/128 , H04L49/90
摘要： A method and system within a data processing system are disclosed for receiving information from a communications network. The data processing system includes a communications adapter, having an adapter memory, and a host memory. The communications adapter is coupled to the communications network, which transmits information to the data processing system in packets including a packet header and packet data. According to the present invention, a portion of a packet of information is received from the communications network at the adapter memory within the communications adapter. The portion of the packet of information includes at least a packet header that specifies a length of the packet of information and a destination address within the host memory. In response to receipt of the portion of the packet of information, a transfer of the packet of information from the adapter memory to the host memory is prepared prior to receipt of a final portion of the packet of information at the adapter memory. The packet of information is then transferred from the adapter memory to addresses within the host memory beginning with the destination address. Since the transfer is prepared before packet receipt is complete, perceived latency is minimized.
摘要翻译：公开了一种用于从通信网络接收信息的数据处理系统内的方法和系统。数据处理系统包括具有适配器存储器和主机存储器的通信适配器。通信适配器耦合到通信网络，其以包括分组报头和分组数据的分组向数据处理系统发送信息。根据本发明，从通信适配器内的适配器存储器处的通信网络接收信息分组的一部分。信息分组的部分至少包括指定信息分组的长度的分组报头和主机存储器内的目的地地址。响应于接收到信息分组的一部分，在适配器存储器上接收到信息分组的最后部分之前准备将信息分组从适配器存储器传送到主机存储器。然后将信息包从适配器存储器转移到主目录内的地址，以目的地址开始。由于在分组接收完成之前准备传输，所以感知到的等待时间被最小化。

3. 发明授权

US5598535A System for selectively and cumulatively grouping packets from different sessions upon the absence of exception condition and sending the packets after preselected time conditions 失效
标题翻译：系统用于在不存在异常情况时，对来自不同会话的数据包进行选择性和累积分组，并在预选的时间条件之后发送数据包
公开(公告)号：US5598535A
公开(公告)日：1997-01-28
申请号：US283889
申请日：1994-08-01
申请人： Brad L. Brech , Gary S. Delp , Albert A. Slane
发明人： Brad L. Brech , Gary S. Delp , Albert A. Slane
IPC分类号： H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： H04L29/06 , H04L69/22 , H04L69/32
摘要： The present invention provides a method and apparatus processing system for enhancing the processing of a plurality of related packets received at a logical unit within a data processing system. A plurality of packets are received at the logical unit. Then each of the plurality of packets are examined and a session identification is obtained for each of the plurality of packets. During a preselected time window, each of the plurality of packets are associated with a group. Each packet in a group has a session identification that is identical to every other packet within the group.
摘要翻译：本发明提供一种用于增强在数据处理系统内以逻辑单元接收的多个相关分组的处理的方法和装置处理系统。在逻辑单元处接收多个分组。然后检查多个分组中的每一个，并且为多个分组中的每个分组获得会话标识。在预选时间窗口期间，多个分组中的每一个与组相关联。组中的每个分组具有与组内的每个其他分组相同的会话标识。

4. 发明授权

US5737638A System for determining plurality of data transformations to be performed upon single set of data during single transfer by examining communication data structure 失效
标题翻译：用于通过检查通信数据结构来确定在单次传送期间对单个数据集合执行的多个数据变换的系统
公开(公告)号：US5737638A
公开(公告)日：1998-04-07
申请号：US502782
申请日：1995-07-14
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
IPC分类号： G06F13/40 , G06F3/00 , G06F15/16
CPC分类号： G06F13/4027
摘要： A method and apparatus are disclosed for providing an inline data service within a data processing system coupled to a communications network. The data processing system includes a host memory. According to the present invention, the apparatus comprises an adapter memory for temporarily storing data communicated between the data processing system and the communications network and a memory access controller, which controls transfers of data between the adapter memory and the host memory. The apparatus further includes means for selectively performing a data transformation on data transferred between the adapter memory and the host memory, wherein the data transformation is performed during a transfer of the data such that data communication latency is reduced. In a second preferred embodiment of the present invention, a multibus data processing system has a processor and a first memory coupled to a first bus and a second memory coupled to a second bus. A bridge adapter, including means for transferring data from the first memory to the second memory and means for selectively performing a data transformation, is coupled between the first and second buses. During transfers of data from the first memory to the second memory, the bridge adapter selectively performs data transformations on the data, such that data processing latency is reduced.
摘要翻译：公开了用于在耦合到通信网络的数据处理系统内提供在线数据服务的方法和装置。数据处理系统包括主机存储器。根据本发明，该装置包括用于临时存储在数据处理系统和通信网络之间传送的数据的适配器存储器和控制适配器存储器和主机存储器之间的数据传输的存储器访问控制器。该装置还包括用于选择性地对在适配器存储器和主机存储器之间传送的数据执行数据变换的装置，其中在数据传送期间执行数据变换，使得数据通信等待时间减少。在本发明的第二优选实施例中，多位数据处理系统具有耦合到第一总线的处理器和第一存储器，以及耦合到第二总线的第二存储器。包括用于将数据从第一存储器传送到第二存储器的装置和用于选择性地执行数据变换的装置的桥接器耦合在第一和第二总线之间。在从第一存储器传输到第二存储器的数据传输期间，桥接器适配器有选择地对数据进行数据转换，从而减少数据处理等待时间。

5. 发明授权

US5537408A apparatus and method for segmentation and time synchronization of the transmission of multimedia data 失效
标题翻译：多媒体数据传输的分段和时间同步的装置和方法
公开(公告)号：US5537408A
公开(公告)日：1996-07-16
申请号：US463207
申请日：1995-06-05
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
IPC分类号： H04N7/26 , G06F17/30 , G06F19/00 , H04J3/06 , H04L12/56 , H04L29/06 , H04L29/08 , H04N7/24 , H04N7/52 , H04N21/2343 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/43 , H04N21/434 , H04N21/4363 , H04N21/438 , H04N21/472 , H04N21/643 , H04N21/845 , H04N21/8547 , H04Q3/00 , H04Q11/04 , H04N5/04
CPC分类号： H04Q11/0478 , H04L29/06 , H04L65/607 , H04N21/234318 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/26208 , H04N21/4307 , H04N21/4341 , H04N21/4363 , H04N21/4381 , H04N21/47202 , H04N21/64307 , H04N21/8456 , H04N21/8547 , H04J3/0632 , H04L2012/5616 , H04L2012/565 , H04L2012/5652 , H04L2012/5664 , H04L2012/5674 , H04L2012/5679 , H04L29/06027 , H04L69/324 , H04L69/326
摘要： Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.
摘要翻译：提供了用于通过分发通信网络发送多媒体数字数据流的方法和装置。多媒体流服务器将多媒体数字数据流分割成第一边界和第二边界上的数据块。第一边界是一组传输系统数据分组，第二边界是包括时间戳的传输系统数据分组。调度器调度分段数据块进行传输。多媒体流服务器解码分段的数据块以定位时间戳，并将所定位的时间戳数据块的传输与由时间戳指示的时间值进行匹配。可以在连接建立时确定传送系统数据包的设定数量，而不是所有会话的预定值。在接收机处，可以提供接收到的多媒体数据的批量处理。

6. 发明授权

US5533021A Apparatus and method for segmentation and time synchronization of the transmission of multimedia data 失效
标题翻译：多媒体数据传输的分段和时间同步的装置和方法
公开(公告)号：US5533021A
公开(公告)日：1996-07-02
申请号：US382905
申请日：1995-02-03
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
IPC分类号： H04N7/26 , G06F17/30 , G06F19/00 , H04J3/06 , H04L12/56 , H04L29/06 , H04L29/08 , H04N7/24 , H04N7/52 , H04N21/2343 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/43 , H04N21/434 , H04N21/4363 , H04N21/438 , H04N21/472 , H04N21/643 , H04N21/845 , H04N21/8547 , H04Q3/00 , H04Q11/04 , H04N7/62
CPC分类号： H04Q11/0478 , H04L29/06 , H04L65/607 , H04N21/234318 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/26208 , H04N21/4307 , H04N21/4341 , H04N21/4363 , H04N21/4381 , H04N21/47202 , H04N21/64307 , H04N21/8456 , H04N21/8547 , H04J3/0632 , H04L2012/5616 , H04L2012/565 , H04L2012/5652 , H04L2012/5664 , H04L2012/5674 , H04L2012/5679 , H04L29/06027 , H04L69/324 , H04L69/326
摘要： Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.
摘要翻译：提供了用于通过分发通信网络发送多媒体数字数据流的方法和装置。多媒体流服务器将多媒体数字数据流分割成第一边界和第二边界上的数据块。第一边界是一组传输系统数据分组，第二边界是包括时间戳的传输系统数据分组。调度器调度分段数据块进行传输。多媒体流服务器解码分段的数据块以定位时间戳，并将所定位的时间戳数据块的传输与由时间戳指示的时间值进行匹配。可以在连接建立时确定传送系统数据包的设定数量，而不是所有会话的预定值。在接收机处，可以提供接收到的多媒体数据的批量处理。

7. 发明授权

US5555387A Method and apparatus for implementing virtual memory having multiple selected page sizes 失效
标题翻译：用于实现具有多个所选页面大小的虚拟存储器的方法和装置
公开(公告)号：US5555387A
公开(公告)日：1996-09-10
申请号：US467266
申请日：1995-06-06
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Kevin G. Plotz , Fadi-Christian E. Safi , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Kevin G. Plotz , Fadi-Christian E. Safi , Albert A. Slane
IPC分类号： G06F12/02 , G06F12/10 , G11B25/04 , G11B33/12 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/10 , G06F12/1009 , G11B25/043 , G06F12/0292 , G06F2212/652 , G11B33/12
摘要： A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.
摘要翻译：提供一种用于实现具有多个选定页面大小的虚拟存储器的方法和装置。虚拟地址包括地图索引和帧偏移量。选择器机构接收虚拟地址帧偏移并生成偏移量和索引。帧映射表索引虚拟地址映射索引和选择器生成的索引，并生成基址。帧映射表生成的基地址和选择器生成的偏移量被组合以提供物理地址。

8. 发明授权

US08484608B2 Base platforms with combined ASIC and FPGA features and process of using the same 失效
公开(公告)号：US08484608B2
公开(公告)日：2013-07-09
申请号：US12576775
申请日：2009-10-09
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

9. 发明授权

US07405476B2 Asymmetric alignment of substrate interconnect to semiconductor die 有权
标题翻译：衬底互连对半导体裸片的不对称对准
公开(公告)号：US07405476B2
公开(公告)日：2008-07-29
申请号：US11260334
申请日：2005-10-27
申请人： Gary S. Delp
发明人： Gary S. Delp
IPC分类号： H01L23/34
CPC分类号： H01L23/5386 , H01L24/81 , H01L25/0655 , H01L2224/24226 , H01L2224/81801 , H01L2224/82 , H01L2224/85 , H01L2224/86 , H01L2924/14 , H01L2924/00
摘要： An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
摘要翻译：一种装置包括第一半导体管芯和至少一个另外的半导体管芯。衬底附接到第一裸片和另一裸片，并且具有将第一裸片上的触点与另一裸片上的相应触点互连的电互连图案。互连图案的特征在基板上具有相对于第一裸片上的触点的位置具有比在另一裸片上的触点的位置更小的公差的位置。

10. 发明授权

US07043703B2 Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers 有权
标题翻译：使用输入/输出关联区域的灵活使用硬宏I / O缓冲区的架构和/或方法
公开(公告)号：US07043703B2
公开(公告)日：2006-05-09
申请号：US10241317
申请日：2002-09-11
申请人： George W. Nation , Gary S. Delp
发明人： George W. Nation , Gary S. Delp
IPC分类号： G06F17/50
CPC分类号： G06F1/22
摘要： An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.
摘要翻译：一种装置，包括（i）一个或多个输入/输出单元，（ii）一个或多个硬宏和（iii）一个或多个输入/输出相关区域。一个或多个输入/输出亲和度区域可以设置在一个或多个输入/输出单元与一个或多个硬宏之间。一个或多个输入/输出关联区域中的每一个可以被定制为（i）第一模式中的电路，以及（ii）在第二模式中在一个或多个输入/输出单元与一个或多个硬宏之间进行路由选择。

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